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Shallow junctions on pillar sidewalls for Sub-100-nm vertical MOSFETs

Shallow junctions on pillar sidewalls for Sub-100-nm vertical MOSFETs
Shallow junctions on pillar sidewalls for Sub-100-nm vertical MOSFETs
A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at VDS = 1 V) and a drain-induced barrier lowering of 0.12 V.
0741-3106
692-695
Gili, E.
6e227036-b8f4-4364-a0ce-28c3899294b8
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Gili, E.
6e227036-b8f4-4364-a0ce-28c3899294b8
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Gili, E., Uchino, T., Hakim, M.M.A., de Groot, C.H., Buiu, O., Hall, S. and Ashburn, Peter (2006) Shallow junctions on pillar sidewalls for Sub-100-nm vertical MOSFETs. IEEE Electron Device Letters, 27 (8), 692-695. (doi:10.1109/LED.2006.879031).

Record type: Article

Abstract

A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at VDS = 1 V) and a drain-induced barrier lowering of 0.12 V.

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Published date: 2006
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 265143
URI: http://eprints.soton.ac.uk/id/eprint/265143
ISSN: 0741-3106
PURE UUID: 09d1389d-46b4-4e76-a1db-1c82c85e6492
ORCID for C.H. de Groot: ORCID iD orcid.org/0000-0002-3850-7101

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Date deposited: 04 Feb 2008 16:31
Last modified: 08 Oct 2019 00:48

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Contributors

Author: E. Gili
Author: T. Uchino
Author: M.M.A. Hakim
Author: C.H. de Groot ORCID iD
Author: O. Buiu
Author: S. Hall
Author: Peter Ashburn

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