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Symbolic Noise Analysis Approach to Computational Hardware Optimization

Ahmadi, Arash and Zwolinski, Mark (2008) Symbolic Noise Analysis Approach to Computational Hardware Optimization At Design Automation Conference (DAC), United States. 09 - 13 Jun 2008. , pp. 391-396.

Record type: Conference or Workshop Item (Paper)


This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for high-level synthesis, which is based on symbolic modeling of the error bounds where the error symbols are considered to be specified with a probability distribution function over a known range. The ability to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated using case studies.

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Published date: 11 June 2008
Additional Information: Event Dates: 9-13 June 2008
Venue - Dates: Design Automation Conference (DAC), United States, 2008-06-09 - 2008-06-13
Keywords: High Level Synthesis, Computational Noise, Word-Length Optimization
Organisations: EEE


Local EPrints ID: 265306
ISBN: 978-1-60558-115-6
PURE UUID: b8737a37-07a2-4726-bfa7-a9496d6606d0
ORCID for Mark Zwolinski: ORCID iD

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Date deposited: 11 Mar 2008 14:02
Last modified: 18 Jul 2017 07:27

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Author: Arash Ahmadi
Author: Mark Zwolinski ORCID iD

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