Ahmadi, Arash and Zwolinski, Mark
Symbolic Noise Analysis Approach to Computational Hardware Optimization
At Design Automation Conference (DAC), United States.
09 - 13 Jun 2008.
- Version of Record
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for high-level synthesis, which is based on symbolic modeling of the error bounds where the error symbols are considered to be specified with a probability distribution function over a known range. The ability to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated using case studies.
Conference or Workshop Item
||Event Dates: 9-13 June 2008
|Venue - Dates:
||Design Automation Conference (DAC), United States, 2008-06-09 - 2008-06-13
||High Level Synthesis, Computational Noise, Word-Length Optimization
|11 June 2008||Published|
||11 Mar 2008 14:02
||17 Apr 2017 19:22
|Further Information:||Google Scholar|
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