Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems


Troya, Alfonso, Maharatna, Koushik, Krstic, Milos, Grass, Eckhard, Jagdhold, Ulrich and Kraemer, Rolf (2008) Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems IEEE Transactions on Circuits and Systems I: Regular Papers, 55, (2), pp. 672-686. (doi:10.1109/TCSI.2007.913732).

Download

[img] PDF tcas1_inner_receiver.pdf - Other
Download (1MB)

Description/Abstract

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics

Item Type: Article
Digital Object Identifier (DOI): doi:10.1109/TCSI.2007.913732
ISSNs: 1549-8328 (print)
Subjects:
Organisations: Electronic & Software Systems
ePrint ID: 265339
Date :
Date Event
March 2008Published
Date Deposited: 27 Mar 2008 12:29
Last Modified: 17 Apr 2017 19:22
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/265339

Actions (login required)

View Item View Item