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Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems

Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems
Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems
In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics
1549-8328
672-686
Troya, Alfonso
ee29f224-5c44-4219-a287-c6f21b1438a7
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Krstic, Milos
bd460841-d42a-4a4b-b440-096f2a09f236
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1
Jagdhold, Ulrich
f6a767c0-c566-487b-9088-beb92b7df066
Kraemer, Rolf
b8e92586-086e-49a2-9df7-483820736f89
Troya, Alfonso
ee29f224-5c44-4219-a287-c6f21b1438a7
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Krstic, Milos
bd460841-d42a-4a4b-b440-096f2a09f236
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1
Jagdhold, Ulrich
f6a767c0-c566-487b-9088-beb92b7df066
Kraemer, Rolf
b8e92586-086e-49a2-9df7-483820736f89

Troya, Alfonso, Maharatna, Koushik, Krstic, Milos, Grass, Eckhard, Jagdhold, Ulrich and Kraemer, Rolf (2008) Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 55 (2), 672-686. (doi:10.1109/TCSI.2007.913732).

Record type: Article

Abstract

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics

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Published date: March 2008
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 265339
URI: https://eprints.soton.ac.uk/id/eprint/265339
ISSN: 1549-8328
PURE UUID: 6655cb8a-3c09-432f-a893-a03ccfa00105

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Date deposited: 27 Mar 2008 12:29
Last modified: 14 Aug 2019 18:53

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