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Improved 6.7GHz CMOS VCO Delay Cell With Up To Seven Octave Tuning Range

Record type: Conference or Workshop Item (Other)

The choice facing most VCO and PLL designers in modern CMOS processes is whether to use LC oscillators with large area and low phase noise, or to use an inverter based all transistor solution with poor phase noise, but much smaller size. This paper makes significant progress in closing the gap in performance between the inverter based and LC approaches. A novel double feedback dual inverter delay cell is proposed that achieves a significantly wider tuning range than previously reported whilst maintaining excellent phase noise performance. A design methodology is presented that includes noise analysis relating transistor level dimensions to the predicted phase noise performance. Two 120nm 1.2V design examples demonstrate that VCOs based on the improved delay cell can reach frequencies in excess of 6.7GHz, and that tuning ranges of over 7 octaves can be achieved.

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Li, Ke, Wilcock, Reuben and Wilson, Peter, (2008) Improved 6.7GHz CMOS VCO Delay Cell With Up To Seven Octave Tuning Range Li, Ke, Wilcock, Reuben and Wilson, Peter (eds.) At 2008 IEEE International Symposium on Circuits and Systems , ISCAS,2008.

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Published date: 19 May 2008
Venue - Dates: 2008 IEEE International Symposium on Circuits and Systems , ISCAS,2008, 2008-05-19
Keywords: Oscillator, Phase Noise, Jitter, CMOS, VCO, Tuning Range
Organisations: EEE


Local EPrints ID: 265847
PURE UUID: 1d06e8b8-7670-4e9f-93c8-0aa1b40503c9

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Date deposited: 05 Jun 2008 08:18
Last modified: 18 Jul 2017 07:23

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Author: Ke Li
Author: Reuben Wilcock
Author: Peter Wilson
Editor: Ke Li
Editor: Reuben Wilcock
Editor: Peter Wilson

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