Normally-off PLED (Planar Localised Electron Device) for non-volatile memory
Normally-off PLED (Planar Localised Electron Device) for non-volatile memory
pp 128-129
Mizuta, Hiroshi
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Nakazato, K.
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Piotrowicz, P. J. A.
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Itoh, K.
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Teshima, T.
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Yamaguchi, K.
817d4eee-95a7-41c3-9d6e-18ca2eac715d
Shimada, T.
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June 1998
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Nakazato, K.
b12e41d3-3527-48ed-9ecd-b38f774ba838
Piotrowicz, P. J. A.
4203806c-bc83-45e2-a8cf-f3605ea17e01
Itoh, K.
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Teshima, T.
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Yamaguchi, K.
817d4eee-95a7-41c3-9d6e-18ca2eac715d
Shimada, T.
a6294be4-3bcc-4436-90e5-70289e2bf523
Mizuta, Hiroshi, Nakazato, K., Piotrowicz, P. J. A., Itoh, K., Teshima, T., Yamaguchi, K. and Shimada, T.
(1998)
Normally-off PLED (Planar Localised Electron Device) for non-volatile memory.
1998 Symposium on VLSI Technology, Honolulu.
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Published date: June 1998
Additional Information:
Event Dates: June 1998
Venue - Dates:
1998 Symposium on VLSI Technology, Honolulu, 1998-05-31
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 266421
URI: http://eprints.soton.ac.uk/id/eprint/266421
PURE UUID: af801f79-27b2-47d6-9e8d-2f37eed08d8a
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Date deposited: 30 Jul 2008 09:15
Last modified: 08 Jan 2022 05:49
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Contributors
Author:
Hiroshi Mizuta
Author:
K. Nakazato
Author:
P. J. A. Piotrowicz
Author:
K. Itoh
Author:
T. Teshima
Author:
K. Yamaguchi
Author:
T. Shimada
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