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Delay Fault Modelling/Simulation using VHDL-AMS in Multi-Vdd Systems

Record type: Conference or Workshop Item (Paper)

With the growing density of Very Large Scale Integrated(VLSI) circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulation at gate level using a Hardware Descriptive Language (HDL) can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results.

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Citation

Zain Ali, Noohul Basheer, Zwolinski, Mark and Ahmadi, Arash (2008) Delay Fault Modelling/Simulation using VHDL-AMS in Multi-Vdd Systems At 26th International Conference on Microelectronics, Serbia. 11 - 14 May 2008.

More information

Published date: 11 May 2008
Additional Information: Event Dates: 11-14 May 2008
Venue - Dates: 26th International Conference on Microelectronics, Serbia, 2008-05-11 - 2008-05-14
Keywords: Fault Modelling, Delay Fault, VHDL-AMS, Multiple-Vdd
Organisations: EEE

Identifiers

Local EPrints ID: 266465
URI: http://eprints.soton.ac.uk/id/eprint/266465
PURE UUID: b3fd8657-5af8-4f7b-bc4a-dbc029712210
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 31 Jul 2008 16:06
Last modified: 18 Jul 2017 07:16

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Contributors

Author: Noohul Basheer Zain Ali
Author: Mark Zwolinski ORCID iD
Author: Arash Ahmadi

University divisions


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