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Path switching: a technique to tolerate dual rail routing imbalances

Record type: Article

Dual Rail Precharge (DRP) circuits, which are theoretically secure against differential power analysis attacks, suffer from an implementation problem: balancing the routing capacitance of differential signals. To solve this, four proposals have been put forward: Divided Wave Dynamic Differential Logic (DWDDL) (Tiri and Verbauwhede in DATE ’04, pp. 246–251, [2004]), FatWire (Tiri and Verbauwhede in Cardis 2004, pp. 143–158, [2004]), Backend Duplication (Guilley et al. in Lecture Notes in Computer Science, vol. 3659, pp. 383–397, [2005]) and Three Phase Dual Rail (Bucci et al. in Lecture Notes in Computer Science, vol. 4249, pp. 232–241, [2006]). Of these, three (DWDDL, FatWire, Backend Duplication) proposals alter the routing mechanism of Standard Place and Route tools, which in turn introduces an additional step. The other proposal introduces a third phase which reduces the system’s performance. In this paper we propose a new countermeasure, Path Switching, to address the routing problem in DRP circuits. From SPICE simulations we show that our proposal does not reveal the secret key for up to 300,000 traces, an increase of 75 times over normal Dual Rail circuits and 3000 times over normal single rail circuits.

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Citation

Baddam, Karthik and Zwolinski, Mark (2008) Path switching: a technique to tolerate dual rail routing imbalances Design Automation for Embedded Systems

More information

Published date: May 2008
Keywords: DPA - Smart card security - Dual rail circuit - Path switching
Organisations: EEE

Identifiers

Local EPrints ID: 266478
URI: http://eprints.soton.ac.uk/id/eprint/266478
PURE UUID: ade76ab8-90f7-4f55-b546-b1caba1359ab
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 01 Aug 2008 12:06
Last modified: 18 Jul 2017 07:16

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Contributors

Author: Karthik Baddam
Author: Mark Zwolinski ORCID iD

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