Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing
Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing
Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lower overhead than the recently proposed Test Point Insertion technique in terms of timing, area and power.
Gate Sizing, Test Cost, Resistive Bridging Faults, Multiple-Vdd designs, Design for Testability
Khursheed, Syed Saqib
df76c622-61ca-45b2-b067-2753f1ac0abf
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Harrod, Peter
d461ce2f-df8a-47ec-a380-167fd3f0bb60
Khursheed, Syed Saqib
df76c622-61ca-45b2-b067-2753f1ac0abf
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Harrod, Peter
d461ce2f-df8a-47ec-a380-167fd3f0bb60
Khursheed, Syed Saqib, Al-Hashimi, Bashir and Harrod, Peter
(2009)
Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing.
Design, Automation and Test in Europe, Nice, France.
(Submitted)
Record type:
Conference or Workshop Item
(Paper)
Abstract
Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lower overhead than the recently proposed Test Point Insertion technique in terms of timing, area and power.
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10.5_2_0595.pdf
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Submitted date: 20 January 2009
Additional Information:
Event Dates: April, 2009
Venue - Dates:
Design, Automation and Test in Europe, Nice, France, 2009-04-01
Keywords:
Gate Sizing, Test Cost, Resistive Bridging Faults, Multiple-Vdd designs, Design for Testability
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 267047
URI: http://eprints.soton.ac.uk/id/eprint/267047
PURE UUID: 6e6ef57a-26f7-4fed-9d84-896a7b887722
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Date deposited: 20 Jan 2009 20:53
Last modified: 14 Mar 2024 08:41
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Contributors
Author:
Syed Saqib Khursheed
Author:
Bashir Al-Hashimi
Author:
Peter Harrod
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