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New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits

New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits
New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits
Estimation of asynchronous circuit performances, such as speed, is one of the major reasons that still keeps that design style undeservedly unpopular. A simple logic simulator would be very useful in overcoming this problem if it is used for evaluating the worst-case delays in the paths of an asynchronous circuit using. In this paper a method for timing analysis of the asynchronous circuits using a VHDL simulator is presented. It is capable to deal with both non-sequential and sequential asynchronous circuit. An appropriate extension of the standard logic simulation process enables all worst-case delays for all paths in a digital circuit to be obtained with only one run of the simulation. High levels of accuracy are achieved using extensive gate modelling while statistical analysis of the results was also used to evaluate part of the parametric yield loss related to the delay. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.
0026-2714
186-198
Sokolovic, Miljana
92569f87-a155-4d69-ac09-a36f80d01085
Litovski, Vanco
c6ee3d8a-0902-4191-a220-ddddbe333091
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Sokolovic, Miljana
92569f87-a155-4d69-ac09-a36f80d01085
Litovski, Vanco
c6ee3d8a-0902-4191-a220-ddddbe333091
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Sokolovic, Miljana, Litovski, Vanco and Zwolinski, Mark (2009) New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits Microelectronics Reliability, 49, (2), pp. 186-198.

Record type: Article

Abstract

Estimation of asynchronous circuit performances, such as speed, is one of the major reasons that still keeps that design style undeservedly unpopular. A simple logic simulator would be very useful in overcoming this problem if it is used for evaluating the worst-case delays in the paths of an asynchronous circuit using. In this paper a method for timing analysis of the asynchronous circuits using a VHDL simulator is presented. It is capable to deal with both non-sequential and sequential asynchronous circuit. An appropriate extension of the standard logic simulation process enables all worst-case delays for all paths in a digital circuit to be obtained with only one run of the simulation. High levels of accuracy are achieved using extensive gate modelling while statistical analysis of the results was also used to evaluate part of the parametric yield loss related to the delay. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.

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Published date: February 2009
Organisations: EEE

Identifiers

Local EPrints ID: 267233
URI: http://eprints.soton.ac.uk/id/eprint/267233
ISSN: 0026-2714
PURE UUID: 20f567d1-6466-4a97-8e52-490c0d0b5d90
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

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Date deposited: 31 Mar 2009 16:24
Last modified: 18 Jul 2017 07:06

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Contributors

Author: Miljana Sokolovic
Author: Vanco Litovski
Author: Mark Zwolinski ORCID iD

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