New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits

Abstract

Estimation of asynchronous circuit performances, such as speed, is one of the major reasons that still keeps that design style undeservedly unpopular. A simple logic simulator would be very useful in overcoming this problem if it is used for evaluating the worst-case delays in the paths of an asynchronous circuit using. In this paper a method for timing analysis of the asynchronous circuits using a VHDL simulator is presented. It is capable to deal with both non-sequential and sequential asynchronous circuit. An appropriate extension of the standard logic simulation process enables all worst-case delays for all paths in a digital circuit to be obtained with only one run of the simulation. High levels of accuracy are achieved using extensive gate modelling while statistical analysis of the results was also used to evaluate part of the parametric yield loss related to the delay. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.

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Identifiers

ORCID for Mark Zwolinski: orcid.org/0000-0002-2230-625X

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