Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement
Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement
Vertical MOSFETs (VMOSFETs) with channel lengths down to 100nm and reduced overlap parasitic capacitance were fabricated using 0.35μm lithography, with only one extra mask step compared to standard CMOS technology. EKV modelling produced reasonable fitting of the DC and AC characteristics for short channel devices. It is noted that achieving sufficiently long channels in vertical pillar devices is difficult and introduces challenges for accurate and scalable compact modelling. The measured peak fT was 7.8 GHz and is significantly limited by high contact resistance and affected by unoptimised junction formation. The study comprehensively reveals structure issues that affect the RF performance. The performance inhibitors have then been optimised using process and device simulation. It is demonstrated that fT and fMAX based on the measurement and numerical simulation, can reach 30.5GHz, and 41GHz respectively.
165-168
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Connor, S.
98c926cf-2c51-4d24-90d2-7d12f3e7e7b0
Bousquet, A.
2c741761-6cbe-4de0-9716-bdcded99c715
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
18 March 2009
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Connor, S.
98c926cf-2c51-4d24-90d2-7d12f3e7e7b0
Bousquet, A.
2c741761-6cbe-4de0-9716-bdcded99c715
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Tan, L., Hakim, M.M.A., Connor, S., Bousquet, A., Redman-White, W., Ashburn, P. and Hall, S.
(2009)
Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement.
10th International Conference on ULtimate Integration of Silicon (ULIS), , Aachen, Germany.
18 - 20 Mar 2009.
.
Record type:
Conference or Workshop Item
(Poster)
Abstract
Vertical MOSFETs (VMOSFETs) with channel lengths down to 100nm and reduced overlap parasitic capacitance were fabricated using 0.35μm lithography, with only one extra mask step compared to standard CMOS technology. EKV modelling produced reasonable fitting of the DC and AC characteristics for short channel devices. It is noted that achieving sufficiently long channels in vertical pillar devices is difficult and introduces challenges for accurate and scalable compact modelling. The measured peak fT was 7.8 GHz and is significantly limited by high contact resistance and affected by unoptimised junction formation. The study comprehensively reveals structure issues that affect the RF performance. The performance inhibitors have then been optimised using process and device simulation. It is demonstrated that fT and fMAX based on the measurement and numerical simulation, can reach 30.5GHz, and 41GHz respectively.
Text
RT-ULIS09-VMOSEKVRF.pdf
- Accepted Manuscript
More information
Published date: 18 March 2009
Additional Information:
Event Dates: 18-20 March
Venue - Dates:
10th International Conference on ULtimate Integration of Silicon (ULIS), , Aachen, Germany, 2009-03-18 - 2009-03-20
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 267243
URI: http://eprints.soton.ac.uk/id/eprint/267243
PURE UUID: 25804de8-1213-4c98-b463-ff536641a84a
Catalogue record
Date deposited: 01 Apr 2009 15:54
Last modified: 14 Mar 2024 08:46
Export record
Contributors
Author:
L. Tan
Author:
M.M.A. Hakim
Author:
S. Connor
Author:
A. Bousquet
Author:
W. Redman-White
Author:
S. Hall
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics