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Asymmetrical IV characteristics and junction regions in implantation defined surround gate vertical MOSFETs

Asymmetrical IV characteristics and junction regions in implantation defined surround gate vertical MOSFETs
Asymmetrical IV characteristics and junction regions in implantation defined surround gate vertical MOSFETs
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in surround gate vertical MOSFETs. The devices have channel lengths defined by implantation, with processes to address some device performance limitations. A ‘junction stop’ process allows optimization of short channel effects by reducing the junction asymmetry but it also induces additional resistance in the top junction. The fillet local oxidation process serves to reduce overlap capacitances however it also induces asymmetry to the top and bottom junction resistances. Non-uniform interface state density down the channel results in asymmetrical subthreshold characteristic. Using a large tilt angle implantation to dope the body can also introduce asymmetry of drain field induced phenomena such as DIBL and impact ionization.
MOS, MOSFET, vertical MOSFET, silicon
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc

Tan, L., Hakim, M.M.A., Uchino, T., Redman-White, W., Ashburn, P. and Hall, S. (2008) Asymmetrical IV characteristics and junction regions in implantation defined surround gate vertical MOSFETs. 9th International Conference on Solid State and Integrated Circuit Technology (ICSICT), China.

Record type: Conference or Workshop Item (Other)

Abstract

This paper investigates the asymmetrical characteristics of junctions and their nearby regions in surround gate vertical MOSFETs. The devices have channel lengths defined by implantation, with processes to address some device performance limitations. A ‘junction stop’ process allows optimization of short channel effects by reducing the junction asymmetry but it also induces additional resistance in the top junction. The fillet local oxidation process serves to reduce overlap capacitances however it also induces asymmetry to the top and bottom junction resistances. Non-uniform interface state density down the channel results in asymmetrical subthreshold characteristic. Using a large tilt angle implantation to dope the body can also introduce asymmetry of drain field induced phenomena such as DIBL and impact ionization.

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Published date: 2008
Venue - Dates: 9th International Conference on Solid State and Integrated Circuit Technology (ICSICT), China, 2008-01-01
Keywords: MOS, MOSFET, vertical MOSFET, silicon
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 267365
URI: https://eprints.soton.ac.uk/id/eprint/267365
PURE UUID: 12e32930-2f25-4a72-a558-0e5bb6a30dd3

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Date deposited: 14 May 2009 10:31
Last modified: 18 Jul 2017 07:05

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