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Inhomogeneous Ni/Ge Schottky barriers due to variation in Fermi-level pinning

Record type: Article

To achieve high performance Ge nMOSFETs it is necessary to reduce the metal/semiconductor Schottky barrier heights at the source and drain. Ni/Ge and NiGe/Ge Schottky barriers are fabricated by electrodeposition using n-type Ge substrates. Current (I)–voltage (V) and capacitance (C)–voltage (V) and low temperature I–V measurements are presented. A high-quality Schottky barrier with extremely low reverse leakage current is revealed. The results are shown to fit an inhomogeneous barrier model for thermionic emission over a Schottky barrier. A mean value of 0.57 eV and a standard deviation of 52 meV is obtained for the Schottky barrier height at room temperature. A likely explanation for the distribution of the Schottky barrier height is the spatial variation of the metal induced gap states at the Ge surface due to a variation in interfacial oxide thickness, which de-pins the Fermi level.

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Citation

Li, Xiaoli, Husain, Muhammad, Kiziroglou, Michail and de Groot, Kees (2009) Inhomogeneous Ni/Ge Schottky barriers due to variation in Fermi-level pinning Microelectronic Engineering, 86, (7-9), pp. 1599-1602.

More information

Published date: June 2009
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 267416
URI: http://eprints.soton.ac.uk/id/eprint/267416
ISSN: 0167-9317
PURE UUID: efd7bfde-f575-482c-8370-0f65bcd1612e
ORCID for Kees de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 29 May 2009 06:35
Last modified: 24 Jul 2017 16:41

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Contributors

Author: Xiaoli Li
Author: Muhammad Husain
Author: Michail Kiziroglou
Author: Kees de Groot ORCID iD

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