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Hardware reduction methodology for 2-dimensional Kurtotic Fast ICA based on algorithmic analysis and architectural symmetry

Hardware reduction methodology for 2-dimensional Kurtotic Fast ICA based on algorithmic analysis and architectural symmetry
Hardware reduction methodology for 2-dimensional Kurtotic Fast ICA based on algorithmic analysis and architectural symmetry
In this paper we propose a hardware reduction methodology through detailed algorithmic analysis and exploiting datapath symmetry for 2-D Kurtotic Fast ICA. The relationship of the hardware saving with respect to input data frame-length and maximum iteration for convergence is also explored. An example architecture following the developed hardware reduction methodology consumes 3.55 mm2 silicon area and 27.1 μW @1 MHz at 1.2 V supply using 0.13 μm standard cell CMOS technology showing the effectiveness of the proposed methodology.
Acharyya, Amit
f7c95a87-04ac-4d13-a74c-0c4d89b1c79c
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Acharyya, Amit
f7c95a87-04ac-4d13-a74c-0c4d89b1c79c
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d

Acharyya, Amit, Maharatna, Koushik and Al-Hashimi, Bashir (2009) Hardware reduction methodology for 2-dimensional Kurtotic Fast ICA based on algorithmic analysis and architectural symmetry. IEEE Workshop on Signal Processing Systems, Finland. 07 - 09 Oct 2009.

Record type: Conference or Workshop Item (Poster)

Abstract

In this paper we propose a hardware reduction methodology through detailed algorithmic analysis and exploiting datapath symmetry for 2-D Kurtotic Fast ICA. The relationship of the hardware saving with respect to input data frame-length and maximum iteration for convergence is also explored. An example architecture following the developed hardware reduction methodology consumes 3.55 mm2 silicon area and 27.1 μW @1 MHz at 1.2 V supply using 0.13 μm standard cell CMOS technology showing the effectiveness of the proposed methodology.

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More information

Published date: 7 October 2009
Additional Information: Event Dates: 7-9 October, 2009
Venue - Dates: IEEE Workshop on Signal Processing Systems, Finland, 2009-10-07 - 2009-10-09
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 267656
URI: https://eprints.soton.ac.uk/id/eprint/267656
PURE UUID: 842f2a88-e681-4068-808c-b1d3b3c9fea5

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Date deposited: 08 Jul 2009 20:56
Last modified: 30 Jul 2019 18:59

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Contributors

Author: Amit Acharyya

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