Defect Tolerance in Hybrid nano/CMOS Architecture using Tagging Mechanism
Defect Tolerance in Hybrid nano/CMOS Architecture using Tagging Mechanism
In this paper we propose two efficient repair techniques for hybrid nano/CMOS architecture to provide high level of defect tolerance at a modest cost.We have applied the proposed techniques to a lookup table(LUT) based Boolean logic approach. The proposed repair techniques are efficient in utilization of spare units and viable for various Boolean logic implementations. We show that the proposed techniques are capable of handling upto 20% defect ratess in hybrid nano/CMOS architecture and upto 14% defect rates for large ISCAS’85 benchmark circuits synthesized into smaller sized LUTs.
Srivastava, Saket
0883e5c1-bc1d-4c46-84a8-a1d9a0a91513
Melouki, Aissa
b14f1adf-1c12-4ed4-ada7-a1c7827c2051
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
30 July 2009
Srivastava, Saket
0883e5c1-bc1d-4c46-84a8-a1d9a0a91513
Melouki, Aissa
b14f1adf-1c12-4ed4-ada7-a1c7827c2051
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Srivastava, Saket, Melouki, Aissa and Al-Hashimi, Bashir
(2009)
Defect Tolerance in Hybrid nano/CMOS Architecture using Tagging Mechanism.
IEEE/ACM Symposium on Nanoscale Architectures, San Francisco, United States.
30 - 31 Jul 2009.
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Conference or Workshop Item
(Other)
Abstract
In this paper we propose two efficient repair techniques for hybrid nano/CMOS architecture to provide high level of defect tolerance at a modest cost.We have applied the proposed techniques to a lookup table(LUT) based Boolean logic approach. The proposed repair techniques are efficient in utilization of spare units and viable for various Boolean logic implementations. We show that the proposed techniques are capable of handling upto 20% defect ratess in hybrid nano/CMOS architecture and upto 14% defect rates for large ISCAS’85 benchmark circuits synthesized into smaller sized LUTs.
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NanoArch_final.pdf
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Published date: 30 July 2009
Additional Information:
Event Dates: July 30-31
Venue - Dates:
IEEE/ACM Symposium on Nanoscale Architectures, San Francisco, United States, 2009-07-30 - 2009-07-31
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 267658
URI: http://eprints.soton.ac.uk/id/eprint/267658
PURE UUID: e5870256-0166-4c05-810e-bfd76a313d74
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Date deposited: 09 Jul 2009 13:28
Last modified: 14 Mar 2024 08:55
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Contributors
Author:
Saket Srivastava
Author:
Aissa Melouki
Author:
Bashir Al-Hashimi
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