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Accelerating CMOS Device Model Evaluation Using Multi-FPGA Systems

Maache, Ahmed, Reeve, Jeff and Zwolinski, Mark (2009) Accelerating CMOS Device Model Evaluation Using Multi-FPGA Systems At Fifth UK Embedded Forum, United Kingdom. 23 - 24 Sep 2009.

Record type: Conference or Workshop Item (Other)

Abstract

Recently, FPGAs have been integrated into HPC clusters in order to boost their computational performance while reducing the power consumption significantly. EDA tools and algorithms are example applications which are demanding more computational power due to the current increase in complexity of analogue and mixed-signal chips. This made transistor-level simulation a growing bottleneck in the integrated circuit development process. This paper discusses the design and implementation of an FPGA-based reconfigurable system to accelerate the SPICE CMOS LEVEL 3 model device evaluation. The preliminary results showed that the system demonstrated an average speed improvement of up to 12x faster than a software implementation running on an Intel 2.0 GHz based workstation. This result is based on a single FPGA implementation. The paper also outlines the design of the multi-FPGA system to accelerate the CMOS model. The proposed system can be attached as a high speed co-processor to boost the SPICE simulation performance.

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More information

Published date: 23 September 2009
Additional Information: Event Dates: 23-24 September 2009
Venue - Dates: Fifth UK Embedded Forum, United Kingdom, 2009-09-23 - 2009-09-24
Organisations: EEE

Identifiers

Local EPrints ID: 268044
URI: http://eprints.soton.ac.uk/id/eprint/268044
PURE UUID: d6ed781f-66a8-4011-b6e4-d5d6bb6d1e41
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 13 Oct 2009 13:59
Last modified: 18 Jul 2017 06:57

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Contributors

Author: Ahmed Maache
Author: Jeff Reeve
Author: Mark Zwolinski ORCID iD

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