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Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell

Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell
Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell
We report a hybrid numerical analysis of the suspended gate silicon nanodot memory (SGSNM) which co-integrates nano-electromechanical systems (NEMS) with silicon MOSFET technology. We propose a new hybrid equivalent circuit model for the SGSNM, in which a parallel-connected variable gate capacitance and variable tunnel resistance model the suspended gate pull-in/pull-out operation and the electron tunnelling process through the tunnelling oxide layer. The signals for the programming, erasing and reading processes are successfully achieved in the circuit level simulation. The programming/erasing speed is found 2.5 ns which is a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications.
hybrid analysis, CMOS-NEMS, Non-volatile memories, Non-Volatile RAM
0167-9317
1284-1286
Garcia Ramirez, Mario
6110a5eb-c5bc-4b1c-9cc3-6569e5ae3259
Tsuchiya, Yoshishige
5a5178c6-b3a9-4e07-b9b2-9a28e49f1dc2
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Garcia Ramirez, Mario
6110a5eb-c5bc-4b1c-9cc3-6569e5ae3259
Tsuchiya, Yoshishige
5a5178c6-b3a9-4e07-b9b2-9a28e49f1dc2
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9

Garcia Ramirez, Mario, Tsuchiya, Yoshishige and Mizuta, Hiroshi (2010) Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell. Microelectronic Engineering, 87 (5-8), 1284-1286. (doi:10.1016/j.mee.2009.10.019).

Record type: Article

Abstract

We report a hybrid numerical analysis of the suspended gate silicon nanodot memory (SGSNM) which co-integrates nano-electromechanical systems (NEMS) with silicon MOSFET technology. We propose a new hybrid equivalent circuit model for the SGSNM, in which a parallel-connected variable gate capacitance and variable tunnel resistance model the suspended gate pull-in/pull-out operation and the electron tunnelling process through the tunnelling oxide layer. The signals for the programming, erasing and reading processes are successfully achieved in the circuit level simulation. The programming/erasing speed is found 2.5 ns which is a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications.

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Published date: May 2010
Keywords: hybrid analysis, CMOS-NEMS, Non-volatile memories, Non-Volatile RAM
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 268271
URI: http://eprints.soton.ac.uk/id/eprint/268271
ISSN: 0167-9317
PURE UUID: f9df4368-b04b-44d9-901a-5d34df4ab5d9

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Date deposited: 27 Nov 2009 10:09
Last modified: 19 Jul 2019 22:16

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