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Scan based methodology for reliable state retention power gating designs

Scan based methodology for reliable state retention power gating designs
Scan based methodology for reliable state retention power gating designs
Power gating is an effective technique for reducing leakage power which involves powering off idle circuits through power switches, but those power-gated circuits which need to retain their states store their data in state retention registers. When power-gated circuits are switched from sleep to active mode, sudden rush of current has the potential of corrupting the stored data in the state retention registers which could be a reliability problem. This paper presents a methodology for improving the reliability of power-gated designs by protecting the integrity of state retention registers through state monitoring and correction. This is achieved by scan chain data encoding and decoding. The methodology is compatible with EDA tools design and power gating control flows. A detailed analysis of the proposed methodology's capability in detecting and correcting errors is given including the area overhead and energy consumption of the protection circuitry. The methodology is validate using FPGA and show that it is possible to correct all single errors with Hamming code and detect all multiple errors with CRC-16 code. To the best of our knowledge this is the first study in the area of reliable power gating designs through state monitoring and correction.
69-74
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506

Yang, Sheng, Al-Hashimi, Bashir, Flynn, David and Khursheed, Saqib (2010) Scan based methodology for reliable state retention power gating designs. Design, Automation and Test in Europe, Dresden, Germany. 08 Mar 2010. pp. 69-74 .

Record type: Conference or Workshop Item (Other)

Abstract

Power gating is an effective technique for reducing leakage power which involves powering off idle circuits through power switches, but those power-gated circuits which need to retain their states store their data in state retention registers. When power-gated circuits are switched from sleep to active mode, sudden rush of current has the potential of corrupting the stored data in the state retention registers which could be a reliability problem. This paper presents a methodology for improving the reliability of power-gated designs by protecting the integrity of state retention registers through state monitoring and correction. This is achieved by scan chain data encoding and decoding. The methodology is compatible with EDA tools design and power gating control flows. A detailed analysis of the proposed methodology's capability in detecting and correcting errors is given including the area overhead and energy consumption of the protection circuitry. The methodology is validate using FPGA and show that it is possible to correct all single errors with Hamming code and detect all multiple errors with CRC-16 code. To the best of our knowledge this is the first study in the area of reliable power gating designs through state monitoring and correction.

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More information

Published date: 8 March 2010
Venue - Dates: Design, Automation and Test in Europe, Dresden, Germany, 2010-03-08 - 2010-03-08
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 268275
URI: http://eprints.soton.ac.uk/id/eprint/268275
PURE UUID: 5d50dd8c-b55f-4d9f-bb05-8aaf94bf567d

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Date deposited: 27 Nov 2009 18:56
Last modified: 31 Oct 2023 04:21

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Contributors

Author: Sheng Yang
Author: Bashir Al-Hashimi
Author: David Flynn
Author: Saqib Khursheed

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