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Optimising Physical Wires Usage in Mesh-based Multi-FPGA Systems using Partition Swapping

Optimising Physical Wires Usage in Mesh-based Multi-FPGA Systems using Partition Swapping
Optimising Physical Wires Usage in Mesh-based Multi-FPGA Systems using Partition Swapping
Recently, FPGAs have been integrated into HPC clusters in order to boost computational performance while reducing power consumption. However, performance and effective logic utilisation is usually limited by the number of inter-device pins and most importantly the interconnection architecture. Mesh interconnection in particular suffers from the pin-limitation problem. The concept of Virtual Wires has been proposed to reduce the impact of this problem by using time-multiplexed physical wires. This paper demonstrates a simple yet effective technique to further reduce the number of the physical wires required by the Virtual Wires and the Mesh architectures by an average of 18% over the original routing algorithms. This technique can be equally applied to exploit the topological properties of any mesh-based architecture.
Maache, Ahmed
bf5bff0a-4bdb-44d1-89ae-df1dc89163c4
Reeve, Jeff
dd909010-7d44-44ea-83fe-a09e4d492618
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Maache, Ahmed, Reeve, Jeff and Zwolinski, Mark (2009) Optimising Physical Wires Usage in Mesh-based Multi-FPGA Systems using Partition Swapping At 21st International Conference on Microelectronics (ICM09), Morocco. 19 - 22 Dec 2009.

Maache, Ahmed, Reeve, Jeff and Zwolinski, Mark (2009) Optimising Physical Wires Usage in Mesh-based Multi-FPGA Systems using Partition Swapping At 21st International Conference on Microelectronics (ICM09), Morocco. 19 - 22 Dec 2009.

Record type: Conference or Workshop Item (Other)

Abstract

Recently, FPGAs have been integrated into HPC clusters in order to boost computational performance while reducing power consumption. However, performance and effective logic utilisation is usually limited by the number of inter-device pins and most importantly the interconnection architecture. Mesh interconnection in particular suffers from the pin-limitation problem. The concept of Virtual Wires has been proposed to reduce the impact of this problem by using time-multiplexed physical wires. This paper demonstrates a simple yet effective technique to further reduce the number of the physical wires required by the Virtual Wires and the Mesh architectures by an average of 18% over the original routing algorithms. This technique can be equally applied to exploit the topological properties of any mesh-based architecture.

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More information

Published date: 19 December 2009
Additional Information: Event Dates: 19-22 December 2009
Venue - Dates: 21st International Conference on Microelectronics (ICM09), Morocco, 2009-12-19 - 2009-12-22
Organisations: EEE

Identifiers

Local EPrints ID: 268355
URI: http://eprints.soton.ac.uk/id/eprint/268355
PURE UUID: 619573f2-d781-45da-b60a-e57c2624176d
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 06 Jan 2010 14:11
Last modified: 18 Jul 2017 06:55

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Contributors

Author: Ahmed Maache
Author: Jeff Reeve
Author: Mark Zwolinski ORCID iD

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