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Improved 6.7 GHz CMOS VCO delay cell with up to seven octave tuning

Record type: Article

The choice facing most VCO and PLL designers in modern CMOS processes is whether to use LC oscillators with large area and low phase noise, or to use an inverter based all transistor solution with poor phase noise, but much smaller size. This paper makes significant progress in closing the gap in performance between the inverter based and LC approaches. A novel double feedback dual inverter delay cell is proposed that achieves a significantly wider tuning range than previously reported whilst maintaining excellent phase noise performance. A design methodology is presented that includes noise analysis relating transistor level dimensions to the predicted phase noise performance. Two 120 nm 1.2 V design examples demonstrate that VCOs based on the improved delay cell can reach frequencies in excess of 6.7 GHz, and that tuning ranges of over 7 octaves can be achieved.

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Citation

Wilcock, R. and Wilson, P. (2008) Improved 6.7 GHz CMOS VCO delay cell with up to seven octave tuning ISCAS 2008. 2008 IEEE International Symposium on Circuits and Systems, pp. 444-7.

More information

Published date: 2008
Additional Information: Imported from ISI Web of Science
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 269356
URI: http://eprints.soton.ac.uk/id/eprint/269356
PURE UUID: 1ca09a0b-22f6-4af5-83c9-318d3b68baee

Catalogue record

Date deposited: 21 Apr 2010 07:46
Last modified: 18 Jul 2017 06:51

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Contributors

Author: R. Wilcock
Author: P. Wilson

University divisions


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