The influence of junction depth on short channel effects in vertical sidewall MOSFETs

Tan, L., Buiu, O., Hall, S., Gill, E., Uchino, T. and Ashburn, P. (2008) The influence of junction depth on short channel effects in vertical sidewall MOSFETs. Solid-State Electronics, 52, 1002-1007. (doi:10.1016/j.sse.2008.03.013).

Abstract

This work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junction depths in vertical MOSFETs, it is necessary to look separately at the electrostatic influence of each junction. In order to suppress short channel effects better, we explore the formation of a shallow drain junction. This is realized by a self-aligned oxide region, or junction stop US) which is formed at the pillar top and acts as a diffusion barrier for shallow junction formation. The benefits of using a JS structure in vertical MOSFETs are demonstrated by simulations which show clearly the effect of asymmetric junctions on SCEs and bulk punch-through. A critical point is identified, where control of SCEs by junction depth is lost and this leads to appropriate junction design in JS vertical sidewall MOSFETs. For a 70 nm channel length the JS structure improves charge sharing by 54 mV and DIBL by 46 mV. For body dopings of 5.0 x 10¹⁷ cm^-3 and 6.0 x 10¹⁷ cm^-3 the JS gives improvements in I-off of 58.7% and 37.8%, respectively, for a given I-on. The inclusion of a retrograde channel gives a further increase in I-on of 586 µA/µm for a body doping of 4.0 x 10¹⁸ cm^-3.

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