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Gate-sizing-based single Vdd test for bridge defects in multi-voltage designs

Khursheed, Syed Saqib, Al-Hashimi, Bashir, Chakrabarty, Krishnendu and Harrod, Peter (2010) Gate-sizing-based single Vdd test for bridge defects in multi-voltage designs IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29, (9), pp. 1409-1421. (doi:10.1109/TCAD.2010.2059310).

Record type: Article

Abstract

The use of multiple voltage settings for dynamic power management is an effective design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% fault coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective gate sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS and ITC benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves single Vdd test, without affecting the fault coverage of the original test. In addition, the proposed technique performs better in terms of timing, area, and power than the recently proposed test point insertion technique. This is the first reported work that achieves single Vdd test for resistive bridge defects, without compromising fault coverage in multi-Vdd designs.

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More information

e-pub ahead of print date: 19 August 2010
Published date: September 2010
Keywords: design for testability gate sizing, multiple-V_{rm dd} designs, resistive bridging faults, test cost
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 270816
URI: http://eprints.soton.ac.uk/id/eprint/270816
PURE UUID: 27140c64-ca96-4654-9cf6-82bf1912edfd

Catalogue record

Date deposited: 09 Apr 2010 12:22
Last modified: 24 Jul 2017 16:40

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Contributors

Author: Syed Saqib Khursheed
Author: Krishnendu Chakrabarty
Author: Peter Harrod

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