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Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement

Tan, L., Hakim, M.M.A., Connor, S., Bousquet, A., Redman-White, W., Ashburn, P. and Hall, S. (2009) Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement At Ultimate Integration on Silicon (ULIS) Conference. 18 - 20 Mar 2009. , pp. 165-168.

Record type: Conference or Workshop Item (Poster)


Vertical MOSFETs (VMOSFETs) with channel lengths down to 100nm and reduced overlap parasitic capacitance were fabricated using 0.35?m lithography, with only one extra mask step compared to standard CMOS technology. EKV modelling produced reasonable fitting of the DC and AC characteristics for short channel devices. It is noted that achieving sufficiently long channels in vertical pillar devices is difficult and introduces challenges for accurate and scalable compact modelling. The measured peak fT was 7.8 GHz and is significantly limited by high contact resistance and affected by unoptimised junction formation. The study comprehensively reveals structure issues that affect the RF performance. The performance inhibitors have then been optimised using process and device simulation. It is demonstrated that fT and fMAX based on the measurement and numerical simulation, can reach 30.5GHz, and 41GHz respectively.

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Published date: March 2009
Additional Information: Event Dates: 18-20 March
Venue - Dates: Ultimate Integration on Silicon (ULIS) Conference, 2009-03-18 - 2009-03-20
Keywords: vertical MOSFET, EKV
Organisations: Nanoelectronics and Nanotechnology


Local EPrints ID: 270868
PURE UUID: 4e04da48-55a6-4801-9213-1164a85d2f5c

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Date deposited: 21 Apr 2010 01:46
Last modified: 18 Jul 2017 06:50

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Author: L. Tan
Author: M.M.A. Hakim
Author: S. Connor
Author: A. Bousquet
Author: W. Redman-White
Author: P. Ashburn
Author: S. Hall

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