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Design Metrics for RTL level estimation of delay variability due to intradie (random) variations

Merrett, Michael, Wang, Yangang, Zwolinski, Mark, Maharatna, Koushik and Alioto, Massimo (2010) Design Metrics for RTL level estimation of delay variability due to intradie (random) variations At ISCAS.

Record type: Conference or Workshop Item (Paper)

Abstract

A simple metric is presented for the accurate prediction of path delay variability within digital circuits synthesised from simple CMOS logic. This allows circuit variability to be assessed at early stages within the design process with minimal computational effort, as extensive Monte Carlo or SSTA runs are not required. This paper introduces the metric and investigates its effectiveness. The final predictions of path delay variability are found to be within 10% of measured path delay variability for a series of test paths synthesised from randomised models of a 130nm technology library. Future work will investigate the effectiveness of the metric for complex cell structures, and will analyse further technology nodes.

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More information

Submitted date: May 2010
Venue - Dates: ISCAS, 0000-02-01
Organisations: Electronic & Software Systems, EEE

Identifiers

Local EPrints ID: 270876
URI: http://eprints.soton.ac.uk/id/eprint/270876
PURE UUID: 955e0f6d-bbc1-4a70-aa1b-d2a6a75328bd
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 21 Apr 2010 09:32
Last modified: 18 Jul 2017 06:50

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Contributors

Author: Michael Merrett
Author: Yangang Wang
Author: Mark Zwolinski ORCID iD
Author: Massimo Alioto

University divisions

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