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Design Metrics for RTL level estimation of delay variability due to intradie (random) variations

Design Metrics for RTL level estimation of delay variability due to intradie (random) variations
Design Metrics for RTL level estimation of delay variability due to intradie (random) variations
A simple metric is presented for the accurate prediction of path delay variability within digital circuits synthesised from simple CMOS logic. This allows circuit variability to be assessed at early stages within the design process with minimal computational effort, as extensive Monte Carlo or SSTA runs are not required. This paper introduces the metric and investigates its effectiveness. The final predictions of path delay variability are found to be within 10% of measured path delay variability for a series of test paths synthesised from randomised models of a 130nm technology library. Future work will investigate the effectiveness of the metric for complex cell structures, and will analyse further technology nodes.
Merrett, Michael
bd23c4c9-5603-4946-8b8e-0f76c8184125
Wang, Yangang
84511804-36d1-44c7-90d4-a18201735a08
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Alioto, Massimo
277c6cef-498f-4c31-bb55-65e5cca1db6b
Merrett, Michael
bd23c4c9-5603-4946-8b8e-0f76c8184125
Wang, Yangang
84511804-36d1-44c7-90d4-a18201735a08
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Alioto, Massimo
277c6cef-498f-4c31-bb55-65e5cca1db6b

Merrett, Michael, Wang, Yangang, Zwolinski, Mark, Maharatna, Koushik and Alioto, Massimo (2010) Design Metrics for RTL level estimation of delay variability due to intradie (random) variations. 2010 IEEE International Symposium on Circuits and Systems, Paris, France. 30 May - 02 Jun 2010. (doi:10.1109/ISCAS.2010.5537133).

Record type: Conference or Workshop Item (Paper)

Abstract

A simple metric is presented for the accurate prediction of path delay variability within digital circuits synthesised from simple CMOS logic. This allows circuit variability to be assessed at early stages within the design process with minimal computational effort, as extensive Monte Carlo or SSTA runs are not required. This paper introduces the metric and investigates its effectiveness. The final predictions of path delay variability are found to be within 10% of measured path delay variability for a series of test paths synthesised from randomised models of a 130nm technology library. Future work will investigate the effectiveness of the metric for complex cell structures, and will analyse further technology nodes.

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Submitted date: May 2010
e-pub ahead of print date: 3 August 2010
Published date: 3 August 2010
Venue - Dates: 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 2010-05-30 - 2010-06-02
Organisations: Electronic & Software Systems, EEE

Identifiers

Local EPrints ID: 270876
URI: https://eprints.soton.ac.uk/id/eprint/270876
PURE UUID: 955e0f6d-bbc1-4a70-aa1b-d2a6a75328bd
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

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Date deposited: 21 Apr 2010 09:32
Last modified: 20 Jul 2019 01:25

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Contributors

Author: Michael Merrett
Author: Yangang Wang
Author: Mark Zwolinski ORCID iD
Author: Massimo Alioto

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