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Parallel Sparse Matrix Solver for Direct Circuit Simulations on FPGAs

Parallel Sparse Matrix Solver for Direct Circuit Simulations on FPGAs
Parallel Sparse Matrix Solver for Direct Circuit Simulations on FPGAs
As part of our effort to parallelise SPICE simulations over multiple FPGAs, we present a parallel FPGA implementation for a sparse matrix solver optimised for execution on a single FPGA node. Our approach combines static pivoting with symbolic analysis to compute an accurate task flow-graph which efficiently exploits parallelism at multiple granularities and sustains high floating-point data rates. The sparse matrix solver is tested with circuit simulation matrices from the University of Florida matrix collection. We report a 10-30X speedup compared to a 2.4 GHz Intel Core Duo processor running UMFPACK, a state-of-the-art sparse matrix solver.
Nechma, Tarek
a0d5c618-5bc1-48a1-8716-f11f206ba3b3
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Reeve, Jeff
dd909010-7d44-44ea-83fe-a09e4d492618
Nechma, Tarek
a0d5c618-5bc1-48a1-8716-f11f206ba3b3
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Reeve, Jeff
dd909010-7d44-44ea-83fe-a09e4d492618

Nechma, Tarek, Zwolinski, Mark and Reeve, Jeff (2010) Parallel Sparse Matrix Solver for Direct Circuit Simulations on FPGAs At ISCAS.

Record type: Conference or Workshop Item (Paper)

Abstract

As part of our effort to parallelise SPICE simulations over multiple FPGAs, we present a parallel FPGA implementation for a sparse matrix solver optimised for execution on a single FPGA node. Our approach combines static pivoting with symbolic analysis to compute an accurate task flow-graph which efficiently exploits parallelism at multiple granularities and sustains high floating-point data rates. The sparse matrix solver is tested with circuit simulation matrices from the University of Florida matrix collection. We report a 10-30X speedup compared to a 2.4 GHz Intel Core Duo processor running UMFPACK, a state-of-the-art sparse matrix solver.

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More information

Submitted date: May 2010
Venue - Dates: ISCAS, 0000-02-01
Organisations: EEE

Identifiers

Local EPrints ID: 270878
URI: http://eprints.soton.ac.uk/id/eprint/270878
PURE UUID: 0a74e679-b4ba-4a43-8587-c81df5d6d274
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 21 Apr 2010 09:37
Last modified: 18 Jul 2017 06:50

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Contributors

Author: Tarek Nechma
Author: Mark Zwolinski ORCID iD
Author: Jeff Reeve

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