Biologically-Inspired Massively-Parallel Architectures - computing beyond a million processors
Biologically-Inspired Massively-Parallel Architectures - computing beyond a million processors
The SpiNNaker project aims to develop parallel computer systems with more than a million embedded processors. The goal of the project is to support largescale simulations of systems of spiking neurons in biological real time, an application that is highly parallel but also places very high loads on the communication infrastructure due to the very high connectivity of biological neurons. The scale of the machine requires fault-tolerance and power-efficiency to influence the design throughout, and the development has resulted in innovation at every level of design, including a self-timed inter-chip communication system that is resistant to glitch-induced deadlock and ‘emergency’ hardware packet re-routing around failed inter-chip links, through to run-time support for functional migration and real-time fault mitigation
Furber, Steve
5060db9f-746b-4af3-b8e0-53c8b5c9f4a0
Brown, Andrew
d41c2ba9-6a1e-44f6-a892-d69895cc4fb8
July 2009
Furber, Steve
5060db9f-746b-4af3-b8e0-53c8b5c9f4a0
Brown, Andrew
d41c2ba9-6a1e-44f6-a892-d69895cc4fb8
Furber, Steve and Brown, Andrew
(2009)
Biologically-Inspired Massively-Parallel Architectures - computing beyond a million processors.
Proc. 9th International Conference on the Application of Concurrency to System Design (ACSD'09),, Augsburg, Germany.
01 - 03 Jul 2009.
Record type:
Conference or Workshop Item
(Paper)
Abstract
The SpiNNaker project aims to develop parallel computer systems with more than a million embedded processors. The goal of the project is to support largescale simulations of systems of spiking neurons in biological real time, an application that is highly parallel but also places very high loads on the communication infrastructure due to the very high connectivity of biological neurons. The scale of the machine requires fault-tolerance and power-efficiency to influence the design throughout, and the development has resulted in innovation at every level of design, including a self-timed inter-chip communication system that is resistant to glitch-induced deadlock and ‘emergency’ hardware packet re-routing around failed inter-chip links, through to run-time support for functional migration and real-time fault mitigation
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PID871138.pdf
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Published date: July 2009
Additional Information:
Event Dates: 1-3 July 2009
Venue - Dates:
Proc. 9th International Conference on the Application of Concurrency to System Design (ACSD'09),, Augsburg, Germany, 2009-07-01 - 2009-07-03
Organisations:
Electronics & Computer Science
Identifiers
Local EPrints ID: 270985
URI: http://eprints.soton.ac.uk/id/eprint/270985
PURE UUID: 8de94327-6f91-4549-a1f2-4ceed4ddda85
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Date deposited: 05 May 2010 13:06
Last modified: 14 Mar 2024 09:19
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Contributors
Author:
Steve Furber
Author:
Andrew Brown
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