A communication infrastructure for a million processor machine
A communication infrastructure for a million processor machine
SpiNNaker (Spiking Neural Network architecture) is a massively parallel computing machine, comprising a million ARM9 cores. These are realised on 50000 chips, 20 cores/chip. While it could be classed as a MIMD machine, there is no unifying bus structure, and there is no attempt to maintain cross-system memory coherence. Inter-core communication is brokered by a fast message-passing system, built in and managed at the hardware level - thus there is an inevitable tension between speed and flexibility. The message passing infrastructure was designed to be fast and have a high bandwidth; a consequence of this design decision is that the effective data payload is only 32 bits/packet. Whilst this is ample for a wide range of applications, when the system is initialising, it is necessary to transport relatively large and sophisticated data structures across the system. This can be slow and cumbersome, and makes some form of internal self-organisation extremely attractive. This is described in outline here.
multi-core, self-organisation
75-76
Brown, Andrew D.
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Furber, Steven B.
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Reeve, Jeff S.
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Wilson, Peter R.
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Zwolinski, Mark
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Chad, John E.
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Plana, Luis
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Lester, David R.
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2010
Brown, Andrew D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Furber, Steven B.
5be90bdd-0b63-4774-9af4-d62df0f2dc27
Reeve, Jeff S.
dd909010-7d44-44ea-83fe-a09e4d492618
Wilson, Peter R.
8a65c092-c197-4f43-b8fc-e12977783cb3
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Chad, John E.
d0a23bec-d31b-4915-bb5d-749d32d6c3c1
Plana, Luis
4953a2dd-d707-4a85-a8c4-7194572163f4
Lester, David R.
f3ca0147-75d3-4a00-8f1e-9a3673d44c7c
Brown, Andrew D., Furber, Steven B., Reeve, Jeff S., Wilson, Peter R., Zwolinski, Mark, Chad, John E., Plana, Luis and Lester, David R.
(2010)
A communication infrastructure for a million processor machine.
Proceedings of the 7th ACM international conference on Computing frontiers.
.
Record type:
Conference or Workshop Item
(Poster)
Abstract
SpiNNaker (Spiking Neural Network architecture) is a massively parallel computing machine, comprising a million ARM9 cores. These are realised on 50000 chips, 20 cores/chip. While it could be classed as a MIMD machine, there is no unifying bus structure, and there is no attempt to maintain cross-system memory coherence. Inter-core communication is brokered by a fast message-passing system, built in and managed at the hardware level - thus there is an inevitable tension between speed and flexibility. The message passing infrastructure was designed to be fast and have a high bandwidth; a consequence of this design decision is that the effective data payload is only 32 bits/packet. Whilst this is ample for a wide range of applications, when the system is initialising, it is necessary to transport relatively large and sophisticated data structures across the system. This can be slow and cumbersome, and makes some form of internal self-organisation extremely attractive. This is described in outline here.
More information
Accepted/In Press date: May 2010
Published date: 2010
Additional Information:
Event Dates: May 2010
Venue - Dates:
Proceedings of the 7th ACM international conference on Computing frontiers, 2010-01-01
Keywords:
multi-core, self-organisation
Organisations:
EEE
Identifiers
Local EPrints ID: 270988
URI: http://eprints.soton.ac.uk/id/eprint/270988
PURE UUID: 3201acec-35ee-4810-9479-e5e604e37f90
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Date deposited: 05 May 2010 13:14
Last modified: 15 Mar 2024 02:39
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Contributors
Author:
Andrew D. Brown
Author:
Steven B. Furber
Author:
Jeff S. Reeve
Author:
Peter R. Wilson
Author:
Mark Zwolinski
Author:
John E. Chad
Author:
Luis Plana
Author:
David R. Lester
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