Compact model extraction issues of nonstandard CMOS compatible vertical MOSFETs
Compact model extraction issues of nonstandard CMOS compatible vertical MOSFETs
Compact models for Vertical MOSFETs (VMOSFETs) with channel lengths from 220nm down to 70nm with frame gate and reduced overlap parasitic capacitances were extracted for both EKV3 and BSIM4. Challenging issues emerged from the extraction process due to the device non-idealities such as those related to channel length estimation, absence of “Through” in the de-embedding structure, non availability of a real “Long” device, high level of interface states with a discrete energy level, asymmetrical gate oxide leakage and parasitic inductance on contact metal strips. The BSIM4 approach proved to be the better, for DC and CV modelling, presumably because of the larger set of fitting parameters for modelling short channel effects, body bias, sub-threshold slopes, bias dependent resistances, gate current and overlap capacitances. The cut-off frequency fT data was successfully fitted with the additional layout parasitics simulated. We suggest that the description of methodology and opinions provided here, should prove useful in the modelling of non-standard devices such as those considered for ‘beyond CMOS’ application.
Tan, L.
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Hakim, M.M.A.
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Connor, S.
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Bousquet, A.
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de Groot, C.H.
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Redman-White, W
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Hall, S.
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Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
17 March 2010
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Connor, S.
98c926cf-2c51-4d24-90d2-7d12f3e7e7b0
Bousquet, A.
2c741761-6cbe-4de0-9716-bdcded99c715
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Redman-White, W
d5376167-c925-460f-8e9c-13bffda8e0bf
Hall, S.
92b937f4-d354-4aab-871b-b0e8b6018a1d
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Tan, L., Hakim, M.M.A., Connor, S., Bousquet, A., de Groot, C.H., Redman-White, W, Hall, S. and Ashburn, P.
(2010)
Compact model extraction issues of nonstandard CMOS compatible vertical MOSFETs.
11th International Conference on ULtimate Integration of Silicon, , Glasgow, United Kingdom.
17 - 19 Mar 2010.
Record type:
Conference or Workshop Item
(Other)
Abstract
Compact models for Vertical MOSFETs (VMOSFETs) with channel lengths from 220nm down to 70nm with frame gate and reduced overlap parasitic capacitances were extracted for both EKV3 and BSIM4. Challenging issues emerged from the extraction process due to the device non-idealities such as those related to channel length estimation, absence of “Through” in the de-embedding structure, non availability of a real “Long” device, high level of interface states with a discrete energy level, asymmetrical gate oxide leakage and parasitic inductance on contact metal strips. The BSIM4 approach proved to be the better, for DC and CV modelling, presumably because of the larger set of fitting parameters for modelling short channel effects, body bias, sub-threshold slopes, bias dependent resistances, gate current and overlap capacitances. The cut-off frequency fT data was successfully fitted with the additional layout parasitics simulated. We suggest that the description of methodology and opinions provided here, should prove useful in the modelling of non-standard devices such as those considered for ‘beyond CMOS’ application.
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Published date: 17 March 2010
Venue - Dates:
11th International Conference on ULtimate Integration of Silicon, , Glasgow, United Kingdom, 2010-03-17 - 2010-03-19
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 271590
URI: http://eprints.soton.ac.uk/id/eprint/271590
PURE UUID: 80735457-3837-4112-9f98-e16eabec4485
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Date deposited: 24 Sep 2010 13:11
Last modified: 11 Dec 2021 03:43
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Contributors
Author:
L. Tan
Author:
M.M.A. Hakim
Author:
S. Connor
Author:
A. Bousquet
Author:
W Redman-White
Author:
S. Hall
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