Tan, L., Hakim, M.M.A., Connor, S., Bousquet, A., de Groot, C.H., Redman-White, W, Hall, S. and Ashburn, P.
Compact model extraction issues of nonstandard CMOS compatible vertical MOSFETs
At 10th International Conference on ULtimate Integration of Silicon (ULIS), United Kingdom.
17 - 19 Mar 2010.
Full text not available from this repository.
Compact models for Vertical MOSFETs (VMOSFETs) with channel lengths from 220nm down to 70nm with frame gate and reduced overlap parasitic capacitances were extracted for both EKV3 and BSIM4. Challenging issues emerged from the extraction process due to the device non-idealities such as those related to channel length estimation, absence of “Through” in the de-embedding structure, non availability of a real “Long” device, high level of interface states with a discrete energy level, asymmetrical gate oxide leakage and parasitic inductance on contact metal strips. The BSIM4 approach proved to be the better, for DC and CV modelling, presumably because of the larger set of fitting parameters for modelling short channel effects, body bias, sub-threshold slopes, bias dependent resistances, gate current and overlap capacitances. The cut-off frequency fT data was successfully fitted with the additional layout parasitics simulated. We suggest that the description of methodology and opinions provided here, should prove useful in the modelling of non-standard devices such as those considered for ‘beyond CMOS’ application.
Conference or Workshop Item
|Venue - Dates:
||10th International Conference on ULtimate Integration of Silicon (ULIS), United Kingdom, 2010-03-17 - 2010-03-19
||Nanoelectronics and Nanotechnology
|17 March 2010||Published|
||24 Sep 2010 13:11
||17 Apr 2017 18:10
|Further Information:||Google Scholar|
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