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Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode

Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode
Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode
This paper presents a new technique, called sub-clock power gating, for reducing leakage power in digital circuits. The proposed technique works concurrently with voltage and frequency scaling and power reduction is achieved by power gating within the clock cycle during active mode unlike traditional power gating which is applied during idle mode. The proposed technique can be implemented using standard EDA tools with simple modifications to the standard power gating design flow. Using a 90nm technology library, the technique is validated using two case studies: 16-bit parallel multiplier and ARM Cortex-M0 microprocessor, provided by our industrial project partner. Compared to designs without sub-clock power gating, in a given power budget, we show that leakage power saved allows 45x and 2.5x improvements in energy efficiency in the case of multiplier and microprocessor, respectively.
power gating, low power, design, leakage power, ARM, voltage scaling, ultra low power
Mistry, Jatin
33aed46c-96bc-4c24-8c7d-a5d404dfd3cc
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Hill, Stephen
0f32be21-7776-4c8d-9cbc-57471f6f64ae
Mistry, Jatin
33aed46c-96bc-4c24-8c7d-a5d404dfd3cc
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Hill, Stephen
0f32be21-7776-4c8d-9cbc-57471f6f64ae

Mistry, Jatin, Al-Hashimi, Bashir, Flynn, David and Hill, Stephen (2011) Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode. Design, Automation and Test in Europe, Grenoble, France. 14 - 18 Mar 2011.

Record type: Conference or Workshop Item (Paper)

Abstract

This paper presents a new technique, called sub-clock power gating, for reducing leakage power in digital circuits. The proposed technique works concurrently with voltage and frequency scaling and power reduction is achieved by power gating within the clock cycle during active mode unlike traditional power gating which is applied during idle mode. The proposed technique can be implemented using standard EDA tools with simple modifications to the standard power gating design flow. Using a 90nm technology library, the technique is validated using two case studies: 16-bit parallel multiplier and ARM Cortex-M0 microprocessor, provided by our industrial project partner. Compared to designs without sub-clock power gating, in a given power budget, we show that leakage power saved allows 45x and 2.5x improvements in energy efficiency in the case of multiplier and microprocessor, respectively.

Text
02.7_3_0279.pdf - Accepted Manuscript
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More information

Published date: 14 March 2011
Additional Information: Event Dates: 14-18 March 2011
Venue - Dates: Design, Automation and Test in Europe, Grenoble, France, 2011-03-14 - 2011-03-18
Keywords: power gating, low power, design, leakage power, ARM, voltage scaling, ultra low power
Organisations: Electronic & Software Systems, EEE

Identifiers

Local EPrints ID: 271768
URI: http://eprints.soton.ac.uk/id/eprint/271768
PURE UUID: 33488cce-d19c-4c18-8b9a-fd330d54bf7a

Catalogue record

Date deposited: 09 Dec 2010 16:23
Last modified: 31 Oct 2023 05:27

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Contributors

Author: Jatin Mistry
Author: Bashir Al-Hashimi
Author: David Flynn
Author: Stephen Hill

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