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Deep level dopant compensated Czochralski silicon substrates for MMICs

Deep level dopant compensated Czochralski silicon substrates for MMICs
Deep level dopant compensated Czochralski silicon substrates for MMICs
The requirement for high resistivity single crystal silicon substrates for microwave monolithic integrated circuit (MMIC) applications above 1 GHz has been underlined in the ITRS Roadmaps, 2007 and 2009. We show that the resistivity of standard Czochralski silicon (Cz-Si) wafers can be enhanced from nominally 50 ?cm to approximately 15 k?cm, measured at about 20 oC using compensation by deep level (DL) impurity states of gold (Au), which was implanted into Cz-Si. We proposed a fully encapsulated Au-doped handle wafer for a SOI wafer configuration to solve the problem of Au contamination of the active wafer. The details have been discussed in our previous publications and a patent. In the present paper, we show significant reduction of RF attenuation in 1-40 GHz range in the DL-doped Si wafers, measured using co-planar waveguide (CPW) test structures fabricated on the material. Notably, the DL-doped wafers have a bi-layer resistivity profile. Our full 3D electromagnetic simulations using Ansys/Ansoft HFSS show significant enhancement of the quality (Q) factor of spiral inductors made on the material.
Mallik, Kanad
013bdafd-6ae0-463e-89a4-6ef1301c5c2f
Abuelgasim, Ahmed
574b647b-e495-42cb-8ed8-952589d79ba3
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
de Groot, Kees
92cd2e02-fcc4-43da-8816-c86f966be90c
Mallik, Kanad
013bdafd-6ae0-463e-89a4-6ef1301c5c2f
Abuelgasim, Ahmed
574b647b-e495-42cb-8ed8-952589d79ba3
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038
de Groot, Kees
92cd2e02-fcc4-43da-8816-c86f966be90c

Mallik, Kanad, Abuelgasim, Ahmed, Ashburn, Peter and de Groot, Kees (2010) Deep level dopant compensated Czochralski silicon substrates for MMICs. ARMMS RF & Microwave Society Conference. (In Press)

Record type: Conference or Workshop Item (Other)

Abstract

The requirement for high resistivity single crystal silicon substrates for microwave monolithic integrated circuit (MMIC) applications above 1 GHz has been underlined in the ITRS Roadmaps, 2007 and 2009. We show that the resistivity of standard Czochralski silicon (Cz-Si) wafers can be enhanced from nominally 50 ?cm to approximately 15 k?cm, measured at about 20 oC using compensation by deep level (DL) impurity states of gold (Au), which was implanted into Cz-Si. We proposed a fully encapsulated Au-doped handle wafer for a SOI wafer configuration to solve the problem of Au contamination of the active wafer. The details have been discussed in our previous publications and a patent. In the present paper, we show significant reduction of RF attenuation in 1-40 GHz range in the DL-doped Si wafers, measured using co-planar waveguide (CPW) test structures fabricated on the material. Notably, the DL-doped wafers have a bi-layer resistivity profile. Our full 3D electromagnetic simulations using Ansys/Ansoft HFSS show significant enhancement of the quality (Q) factor of spiral inductors made on the material.

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More information

Accepted/In Press date: November 2010
Additional Information: Event Dates: November 2010
Venue - Dates: ARMMS RF & Microwave Society Conference, 2010-11-01
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 271787
URI: http://eprints.soton.ac.uk/id/eprint/271787
PURE UUID: 7ac12fab-3ef4-4c01-8a3f-c6112a5c3b57
ORCID for Kees de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 15 Dec 2010 11:14
Last modified: 06 Jun 2018 12:50

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Contributors

Author: Kanad Mallik
Author: Ahmed Abuelgasim
Author: Peter Ashburn
Author: Kees de Groot ORCID iD

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