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Simplified Logic Design Methodology for Fuzzy Membership Function based Robust Detection of Maternal Modulus Maxima Location : a Low Complexity Fetal ECG Extraction Architecture for Mobile Health Monitoring Systems

Simplified Logic Design Methodology for Fuzzy Membership Function based Robust Detection of Maternal Modulus Maxima Location : a Low Complexity Fetal ECG Extraction Architecture for Mobile Health Monitoring Systems
Simplified Logic Design Methodology for Fuzzy Membership Function based Robust Detection of Maternal Modulus Maxima Location : a Low Complexity Fetal ECG Extraction Architecture for Mobile Health Monitoring Systems
This paper proposes a simplified logic design methodology for the fuzzy membership function used for robust and reliable detection of modulus-maxima locations in wavelet domain for fetal ECG extraction from the abdominal composite ECG signal. This simplification is achieved by exploiting the inherent time-position information of the wavelet coefficients decomposed at different resolution levels. Subsequently, a low complexity VLSI architecture for Fetal ECG extraction is presented which is designed using the recently proposed memory-efficient, multiplierless Discrete Wavelet Transform method. The generic memory model within this architecture will provide the flexibility to configure the on-chip memory with any type of orthonormal wavelets suitable for different applications. Total synthesized cell area of the proposed architecture is 14.2 mm2 and power consumption is 101.5 µW at 1.2V @ 1 MHz frequency using 0.13 µm standard cell technology. The proposed architecture is targeted for the personalized health monitoring applications within a mobile home-care medical device in the resource constrained environment.
Wavelet Transform, Fetal ECG Extraction, Low Power Design, VLSI Architecture
Acharyya, Amit
f7c95a87-04ac-4d13-a74c-0c4d89b1c79c
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Tudugalle, Hasitha
bea144aa-c3bb-4ec0-a513-986fc39b875d
Acharyya, Amit
f7c95a87-04ac-4d13-a74c-0c4d89b1c79c
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Tudugalle, Hasitha
bea144aa-c3bb-4ec0-a513-986fc39b875d

Acharyya, Amit, Maharatna, Koushik, Al-Hashimi, Bashir and Tudugalle, Hasitha (2011) Simplified Logic Design Methodology for Fuzzy Membership Function based Robust Detection of Maternal Modulus Maxima Location : a Low Complexity Fetal ECG Extraction Architecture for Mobile Health Monitoring Systems. IEEE International Symposium on Circuits and Systems, Brazil. 15 - 18 May 2011.

Record type: Conference or Workshop Item (Other)

Abstract

This paper proposes a simplified logic design methodology for the fuzzy membership function used for robust and reliable detection of modulus-maxima locations in wavelet domain for fetal ECG extraction from the abdominal composite ECG signal. This simplification is achieved by exploiting the inherent time-position information of the wavelet coefficients decomposed at different resolution levels. Subsequently, a low complexity VLSI architecture for Fetal ECG extraction is presented which is designed using the recently proposed memory-efficient, multiplierless Discrete Wavelet Transform method. The generic memory model within this architecture will provide the flexibility to configure the on-chip memory with any type of orthonormal wavelets suitable for different applications. Total synthesized cell area of the proposed architecture is 14.2 mm2 and power consumption is 101.5 µW at 1.2V @ 1 MHz frequency using 0.13 µm standard cell technology. The proposed architecture is targeted for the personalized health monitoring applications within a mobile home-care medical device in the resource constrained environment.

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Published date: 15 May 2011
Additional Information: Event Dates: 15-18 May, 2011
Venue - Dates: IEEE International Symposium on Circuits and Systems, Brazil, 2011-05-15 - 2011-05-18
Keywords: Wavelet Transform, Fetal ECG Extraction, Low Power Design, VLSI Architecture
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 271868
URI: https://eprints.soton.ac.uk/id/eprint/271868
PURE UUID: 298d4e40-2cfb-45ff-bf39-176d579e175e

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Date deposited: 04 Jan 2011 22:01
Last modified: 03 Jul 2018 16:31

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