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Improved DFT for Testing Power Switches

Improved DFT for Testing Power Switches
Improved DFT for Testing Power Switches
Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off, when testing power switches using available DFT solutions. This may either lead to false test (false-fail or false-pass) or long test time. This problem is addressed through a simple and effective DFT solution to reduce the discharge time. The proposed DFT solution has been validated through SPICE simulation and shows an improvement in discharge time of at least 28-times, based on a number of ISCAS benchmarks synthesized with a 90-nm gate library.
Sleep transistor, power switch, leakage power management, test time overhead, DFT, design for test
Khursheed, Syed Saqib
df76c622-61ca-45b2-b067-2753f1ac0abf
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Huang, Xiaoyu
e5d072b9-2503-4462-a11b-59565c7dd462
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Khursheed, Syed Saqib
df76c622-61ca-45b2-b067-2753f1ac0abf
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Huang, Xiaoyu
e5d072b9-2503-4462-a11b-59565c7dd462
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c

Khursheed, Syed Saqib, Yang, Sheng, Al-Hashimi, Bashir, Huang, Xiaoyu and Flynn, David (2011) Improved DFT for Testing Power Switches. 16th IEEE European Test Symposium (ETS 2011), Trondheim, Norway. 23 - 27 May 2011.

Record type: Conference or Workshop Item (Paper)

Abstract

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off, when testing power switches using available DFT solutions. This may either lead to false test (false-fail or false-pass) or long test time. This problem is addressed through a simple and effective DFT solution to reduce the discharge time. The proposed DFT solution has been validated through SPICE simulation and shows an improvement in discharge time of at least 28-times, based on a number of ISCAS benchmarks synthesized with a 90-nm gate library.

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More information

Published date: 15 February 2011
Additional Information: Event Dates: 23-27 May, 2011
Venue - Dates: 16th IEEE European Test Symposium (ETS 2011), Trondheim, Norway, 2011-05-23 - 2011-05-27
Keywords: Sleep transistor, power switch, leakage power management, test time overhead, DFT, design for test
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 272031
URI: http://eprints.soton.ac.uk/id/eprint/272031
PURE UUID: 23f56606-7c4f-468b-b72b-def6be52123d

Catalogue record

Date deposited: 15 Feb 2011 19:18
Last modified: 31 Oct 2023 05:37

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Contributors

Author: Syed Saqib Khursheed
Author: Sheng Yang
Author: Bashir Al-Hashimi
Author: Xiaoyu Huang
Author: David Flynn

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