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The Analysis of the Implementation of Concurrent Error Detection in Multi-Level Flash Memories

Halak, Basel and Russell, Gordon (2006) The Analysis of the Implementation of Concurrent Error Detection in Multi-Level Flash Memories At IEEE European Test Symposium.

Record type: Conference or Workshop Item (Poster)

Abstract

The increasing demands for high density and low cost non-volatile storage media are driving the technology development of flash memories. A novel solution to increase its storage density and reduce its cost per bit is to adopt the Multilevel Cell technologies. This approach consists of storing several bits in one transistor. According to ITRS report in 2004 the number of bits which can be stored in one cell will be 8 in 2010. One disadvantage of this approach is the degradation in the memory reliability therefore an efficient testing method which has some error correction ability should be used for ML-flash memories in order to allow its use in reliable systems. This paper investigates the applicability and overheads of a concurrent testing technique based on symbol error correcting codes on multilevel flash memories. This method is explained and testing schemes of for 4, 16, 32, 64 level flash memories are described and simulated in VHDL. Area overheads and timing impact of this method are also discussed

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More information

Published date: 6 June 2006
Venue - Dates: IEEE European Test Symposium, 2006-06-06
Organisations: EEE

Identifiers

Local EPrints ID: 272156
URI: http://eprints.soton.ac.uk/id/eprint/272156
PURE UUID: 218cf385-20bb-4efc-b6f0-774fddb68401

Catalogue record

Date deposited: 06 Apr 2011 12:09
Last modified: 18 Jul 2017 06:33

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Contributors

Author: Basel Halak
Author: Gordon Russell

University divisions

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