Acceleration of Functional Validation using GPGPU

Logic simulation of a VLSI chip is a computationally intensive process. There exists an urgent need to map functional validation algorithms onto parallel architectures to aid hardware designers in meeting time-to-market constraints. In this paper, we propose three novel methods for logic simulation of combinational circuits on GPGPUs. Initial experiments run on two methods using benchmark circuits using NVIDIA GPGPUs suggest that these methods can be used for accelerating the EDA design flow process.

Practical/ benchmark testing, combinational circuits, computer graphic equipment, coprocessors, electronic design automation, integrated logic circuits, logic simulation, parallel architectures, time to market, VLSI/ functional validation, GPGPU, VLSI chip, parallel architecture, time-to-market, combinational circuit, benchmark circuit, EDA design flow process, general purpose graphics processing units/ B1265A Digital circuit design, modelling and testing, B1265B Logic circuits, B1265F Microprocessors and microcomputers, B2570A Semiconductor integrated circuit design, layout, C7410D Electronic engineering computing, C5210B Computer-aided logic design, C5130 Microprocessor chips, C5120 Logic and switching circuits, C5220P Parallel architecture

978-1-4244-9357-9

211-216

Suresh, L.

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Rameshan, N.

2ecb93a4-6533-42a7-a773-ccf50ebca70c

Gaur, M.S.

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Zwolinski, M.

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Laxmi, V.

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January 2011

Suresh, L.

2a2e12d2-af48-4bbe-864b-adfedcbefe7c

Rameshan, N.

2ecb93a4-6533-42a7-a773-ccf50ebca70c

Gaur, M.S.

d4a63afd-c0a0-479e-9a17-e93d99630bd3

Zwolinski, M.

adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Laxmi, V.

8ba515fc-a1f3-4685-8fac-3519ae9de905

Suresh, L., Rameshan, N., Gaur, M.S., Zwolinski, M. and Laxmi, V. (2011) Acceleration of Functional Validation using GPGPU. Proceedings of the 2011 IEEE 6th International Workshop on Electronic Design, Test and Application (DELTA 2011). pp. 211-216 .

Record type: Conference or Workshop Item (Other)

Abstract

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More information

Published date: January 2011

Additional Information: 2011 IEEE 6th International Workshop on Electronic Design, Test and Application (DELTA 2011), 17-19 January 2011, Queenstown, New Zealand

Venue - Dates: Proceedings of the 2011 IEEE 6th International Workshop on Electronic Design, Test and Application (DELTA 2011), 2011-01-01

Keywords: Practical/ benchmark testing, combinational circuits, computer graphic equipment, coprocessors, electronic design automation, integrated logic circuits, logic simulation, parallel architectures, time to market, VLSI/ functional validation, GPGPU, VLSI chip, parallel architecture, time-to-market, combinational circuit, benchmark circuit, EDA design flow process, general purpose graphics processing units/ B1265A Digital circuit design, modelling and testing, B1265B Logic circuits, B1265F Microprocessors and microcomputers, B2570A Semiconductor integrated circuit design, layout, C7410D Electronic engineering computing, C5210B Computer-aided logic design, C5130 Microprocessor chips, C5120 Logic and switching circuits, C5220P Parallel architecture

Organisations: EEE