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Evaluation of dynamic voltage and frequency scaling as a differential power analysis countermeasure

Evaluation of dynamic voltage and frequency scaling as a differential power analysis countermeasure
Evaluation of dynamic voltage and frequency scaling as a differential power analysis countermeasure
Differential power analysis (DPA) attack is a major concern for secure embedded devices (Ravi et al., 2004)-(Ors et al., 2004). Currently proposed countermeasures (Pramstaller, 2005)-(Tin and Verbauwhede, 2004) to prevent DPA imposes significant area, power and performance overheads. In addition they either require special standard cell library and design flows or algorithmic modifications. Recently, random dynamic voltage and frequency scaling (RDVFS) has been proposed (Yang et al., 2005) as a DPA countermeasure, which has less area, power and performance overheads and it does not require special cell library nor design flows nor algorithmic modifications. However, in a synchronous digital circuit, the operating frequency can be detected by monitoring glitches on the power line. In this paper, the authors show that using this information, it is possible to mount a DPA attack on circuits employing RDVFS countermeasure. The authors propose an alternative technique which only varies the supply voltage randomly. Experimental results on AES core with SPICE level simulations show that our proposed method significantly weakens the DPA attack by reducing the correlation of power to processed data.
Practical, Experimental/ cryptography, digital circuits, power supply circuits, scaling circuits, SPICE/ dynamic voltage scaling, dynamic frequency scaling, differential power analysis, embedded devices, DPA countermeasure, synchronous digital circuit, AES core, SPICE level simulations/ B6120D Cryptography, B1265B Logic circuits, C5120 Logic and switching circuits
Baddam, K.
3585fe86-aa09-4cff-9b3a-c02e91c403e3
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Baddam, K.
3585fe86-aa09-4cff-9b3a-c02e91c403e3
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Baddam, K. and Zwolinski, M. (2007) Evaluation of dynamic voltage and frequency scaling as a differential power analysis countermeasure. 2007 20th International Conference on VLSI Design.

Record type: Conference or Workshop Item (Other)

Abstract

Differential power analysis (DPA) attack is a major concern for secure embedded devices (Ravi et al., 2004)-(Ors et al., 2004). Currently proposed countermeasures (Pramstaller, 2005)-(Tin and Verbauwhede, 2004) to prevent DPA imposes significant area, power and performance overheads. In addition they either require special standard cell library and design flows or algorithmic modifications. Recently, random dynamic voltage and frequency scaling (RDVFS) has been proposed (Yang et al., 2005) as a DPA countermeasure, which has less area, power and performance overheads and it does not require special cell library nor design flows nor algorithmic modifications. However, in a synchronous digital circuit, the operating frequency can be detected by monitoring glitches on the power line. In this paper, the authors show that using this information, it is possible to mount a DPA attack on circuits employing RDVFS countermeasure. The authors propose an alternative technique which only varies the supply voltage randomly. Experimental results on AES core with SPICE level simulations show that our proposed method significantly weakens the DPA attack by reducing the correlation of power to processed data.

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Published date: January 2007
Additional Information: 2007 20th International Conference on VLSI Design, 6-10 January 2007, Bangalore, India
Venue - Dates: 2007 20th International Conference on VLSI Design, 2007-01-01
Keywords: Practical, Experimental/ cryptography, digital circuits, power supply circuits, scaling circuits, SPICE/ dynamic voltage scaling, dynamic frequency scaling, differential power analysis, embedded devices, DPA countermeasure, synchronous digital circuit, AES core, SPICE level simulations/ B6120D Cryptography, B1265B Logic circuits, C5120 Logic and switching circuits
Organisations: EEE

Identifiers

Local EPrints ID: 272300
URI: https://eprints.soton.ac.uk/id/eprint/272300
PURE UUID: 81dd8630-3702-4045-8195-a221e8c02ece
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 17 May 2011 17:18
Last modified: 19 Jul 2019 01:21

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