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Hybrid Numerical Analysis of a high-speed non-volatile Suspended Gate Silicon Nanodot Memory

Hybrid Numerical Analysis of a high-speed non-volatile Suspended Gate Silicon Nanodot Memory
Hybrid Numerical Analysis of a high-speed non-volatile Suspended Gate Silicon Nanodot Memory
We present a hybrid numerical analysis of a high-speed and non-volatile suspended gate silicon nanodot memory (SGSNM) which co-integrates a nano-electromechanical (NEM) control gate with a MOSFET as a readout element and silicon nanodots as a floating gate. A hybrid NEM-MOS circuit simulation is developed by taking account of the pull-in/pull-out operation of the suspended gate and electron tunnelling processes through the tunnel oxide layer as behavioural models. The signals for programming, erasing and reading are successfully achieved at circuit level simulation. The programming and erasing times are found as short as 2.5 nsec for a SGSNM with a 1-?m-long suspended gate, which is a summation of the mechanical pull-in/pull-out times and the tunnel charging/discharging times.
Non- Volatile Memory, NEMS, Hybrid Circuit Analysis, Suspended Gate Structure
1569-8025
248-257
Garcia Ramirez, Mario
6110a5eb-c5bc-4b1c-9cc3-6569e5ae3259
Tsuchiya, Yoshishige
5a5178c6-b3a9-4e07-b9b2-9a28e49f1dc2
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Garcia Ramirez, Mario
6110a5eb-c5bc-4b1c-9cc3-6569e5ae3259
Tsuchiya, Yoshishige
5a5178c6-b3a9-4e07-b9b2-9a28e49f1dc2
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9

Garcia Ramirez, Mario, Tsuchiya, Yoshishige and Mizuta, Hiroshi (2011) Hybrid Numerical Analysis of a high-speed non-volatile Suspended Gate Silicon Nanodot Memory. Journal of Computational Electronics, 10 (1), 248-257. (doi:10.1007/s10825-011-0361-z).

Record type: Article

Abstract

We present a hybrid numerical analysis of a high-speed and non-volatile suspended gate silicon nanodot memory (SGSNM) which co-integrates a nano-electromechanical (NEM) control gate with a MOSFET as a readout element and silicon nanodots as a floating gate. A hybrid NEM-MOS circuit simulation is developed by taking account of the pull-in/pull-out operation of the suspended gate and electron tunnelling processes through the tunnel oxide layer as behavioural models. The signals for programming, erasing and reading are successfully achieved at circuit level simulation. The programming and erasing times are found as short as 2.5 nsec for a SGSNM with a 1-?m-long suspended gate, which is a summation of the mechanical pull-in/pull-out times and the tunnel charging/discharging times.

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Published date: May 2011
Keywords: Non- Volatile Memory, NEMS, Hybrid Circuit Analysis, Suspended Gate Structure
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 272344
URI: https://eprints.soton.ac.uk/id/eprint/272344
ISSN: 1569-8025
PURE UUID: caa27e2b-573b-47ed-ba28-9c937c291c3c

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Date deposited: 25 May 2011 10:58
Last modified: 19 Jul 2019 22:09

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Contributors

Author: Mario Garcia Ramirez
Author: Yoshishige Tsuchiya
Author: Hiroshi Mizuta

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