A Fast and Accurate Process Variation-aware Modeling Technique for Resistive Bridge Defects
A Fast and Accurate Process Variation-aware Modeling Technique for Resistive Bridge Defects
Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using BSIM4 transistor model. To speedup the computation time and without compromising simulation accuracy (achieved through BSIM4) two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE.
Zhong, Shida
8c250ea8-d473-4aed-b3c1-4fbcb17039b6
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Zhong, Shida
8c250ea8-d473-4aed-b3c1-4fbcb17039b6
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Zhong, Shida, Khursheed, Saqib and Al-Hashimi, Bashir
(2011)
A Fast and Accurate Process Variation-aware Modeling Technique for Resistive Bridge Defects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
(Submitted)
Abstract
Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using BSIM4 transistor model. To speedup the computation time and without compromising simulation accuracy (achieved through BSIM4) two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE.
Text
A_Fast_and_Accurate_Process_Variation-aware_Modeling_Technique_for_Resistive_Bridge_Defects.pdf
- Accepted Manuscript
More information
Submitted date: 5 July 2011
Organisations:
Electronic & Software Systems, EEE
Identifiers
Local EPrints ID: 272539
URI: http://eprints.soton.ac.uk/id/eprint/272539
PURE UUID: 540fde59-8ab4-4932-b9d0-d36ae327a2c5
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Date deposited: 05 Jul 2011 13:21
Last modified: 31 Mar 2020 16:37
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Contributors
Author:
Shida Zhong
Author:
Saqib Khursheed
Author:
Bashir Al-Hashimi
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