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On Proving with Event-B that a Pipelined Processor Model Implements its ISA Specification

On Proving with Event-B that a Pipelined Processor Model Implements its ISA Specification
On Proving with Event-B that a Pipelined Processor Model Implements its ISA Specification
Microprocessor pipelining is a well-established technique that improves performance and reduces power consumption by overlapping in- struction execution. Verifying, however, that an implementation meets this ISA specification is complex and time-consuming. One of the key verification issues that must be addressed is that of overlapping instruc- tion execution. This can introduce hazards where, for instance, a new instruction reads the value from a register which will be written by an earlier instruction that has not yet completed. Using Event-B’s support for refinement with automated proof, a method is explored where the ab- stract machine represents directly an instruction from the ISA that spec- ifies the e
Colley, John
53af70fc-be33-48c1-bd8e-959e2b77b3e1
Butler, Michael
54b9c2c7-2574-438e-9a36-6842a3d53ed0
Colley, John
53af70fc-be33-48c1-bd8e-959e2b77b3e1
Butler, Michael
54b9c2c7-2574-438e-9a36-6842a3d53ed0

Colley, John and Butler, Michael (2009) On Proving with Event-B that a Pipelined Processor Model Implements its ISA Specification At Dagstuhl Seminar on Refinement Based Methods for the Construction of Dependable Systems.

Record type: Conference or Workshop Item (Paper)

Abstract

Microprocessor pipelining is a well-established technique that improves performance and reduces power consumption by overlapping in- struction execution. Verifying, however, that an implementation meets this ISA specification is complex and time-consuming. One of the key verification issues that must be addressed is that of overlapping instruc- tion execution. This can introduce hazards where, for instance, a new instruction reads the value from a register which will be written by an earlier instruction that has not yet completed. Using Event-B’s support for refinement with automated proof, a method is explored where the ab- stract machine represents directly an instruction from the ISA that spec- ifies the e

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More information

Published date: 2009
Additional Information: Event Dates: September 2009
Venue - Dates: Dagstuhl Seminar on Refinement Based Methods for the Construction of Dependable Systems, 2009-09-01
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 272590
URI: http://eprints.soton.ac.uk/id/eprint/272590
PURE UUID: 469430b8-50f7-48ef-aec4-02717363237a
ORCID for Michael Butler: ORCID iD orcid.org/0000-0003-4642-5373

Catalogue record

Date deposited: 22 Jul 2011 08:02
Last modified: 18 Jul 2017 06:22

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Contributors

Author: John Colley
Author: Michael Butler ORCID iD

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