Double data rate interface
Double data rate interface
The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.
US Patent 7847608B2
7 December 2010
Redman-White, William
d5376167-c925-460f-8e9c-13bffda8e0bf
Redman-White, William
(Inventors)
(2010)
Double data rate interface.
US Patent 7847608B2.
Abstract
The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.
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More information
Published date: 7 December 2010
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 337761
URI: http://eprints.soton.ac.uk/id/eprint/337761
PURE UUID: c4aa9375-15fc-405f-bfcd-fefe4ea64327
Catalogue record
Date deposited: 02 May 2012 13:53
Last modified: 14 Mar 2024 10:58
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Contributors
Inventor:
William Redman-White
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