Radiation hardening by design: a novel gate level approach

Soft errors induced by radiation, causing malfunctions in electronic systems and circuits, have become one of the most challenging issues that impact the reliability of the modern processors even in sea-level applications. In this paper we present two novel radiation-hardening techniques at Gate-level. We present a Single-Event-Upset (SEU) tolerant Flip-Flop design with 38% less power overhead and 25% less area overhead at 65nm technology comparing to the conventional Triple Modular Redundancy (TMR) for Flip-Flop design. We also present an SEU-tolerant Clock-Gating scheme with less than 50% area-power overheads and no performance penalty comparing to the conventional TMR for clock-gating. Our simulations show that the proposed schemes can recover from SEU errors in 99% of the cases

SEU tolerant flip-flop design, SEU-tolerant clock-gating scheme, TMR, area-power overheads, electronic circuits, electronic systems, gate level approach, radiation-hardening techniques, sea-level applications, single-event-upset tolerant flip-flop design, size 65 nm, triple modular redundancy, flip-flops, integrated circuit reliability, logic design, radiation hardening (electronics)

978-1-4577-0598-4

10.1109/AHS.2011.5963919

74-79

IEEE

Ghahroodi, Massoud

23d6371c-f047-4afe-bdc7-f419654c8c88

Zwolinski, Mark

adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Ozer, Emre

07d738b5-0b1c-4291-8284-9179c191c3d2

June 2011

Ghahroodi, Massoud

23d6371c-f047-4afe-bdc7-f419654c8c88

Zwolinski, Mark

adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Ozer, Emre

07d738b5-0b1c-4291-8284-9179c191c3d2

Ghahroodi, Massoud, Zwolinski, Mark and Ozer, Emre (2011) Radiation hardening by design: a novel gate level approach. In Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE. pp. 74-79 . (doi:10.1109/AHS.2011.5963919).

Record type: Conference or Workshop Item (Paper)

Abstract

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More information

Published date: June 2011

Venue - Dates: Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), San Diego Country Estates, United States, 2011-06-06 - 2011-06-09

Keywords: SEU tolerant flip-flop design, SEU-tolerant clock-gating scheme, TMR, area-power overheads, electronic circuits, electronic systems, gate level approach, radiation-hardening techniques, sea-level applications, single-event-upset tolerant flip-flop design, size 65 nm, triple modular redundancy, flip-flops, integrated circuit reliability, logic design, radiation hardening (electronics)

Organisations: EEE