Processing with a million cores
Processing with a million cores
Traditionally, the performance-limiting attributes of a multi-processor machine are memory bandwidth, the need to maintain state coherence, and simple synchronisation issues, or some combination of these. As the system size increases, so too does the relative cost overhead of solving these problems. The SpiNNaker engine is a million core system with over eight terabytes of distributed memory whose fundamental design axioms neatly sidestep these problems: the processors are not synchronised, the memory is not coherent, and the inter-processor communication is non-deterministic. How, then, can we perform meaningful computations with this architecture?
978-1-61499-040-6
327-334
Brown, Andrew D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Reeve, Jeffrey
dd909010-7d44-44ea-83fe-a09e4d492618
Furber, Stephen
e9e61fb3-2bb8-45be-9f39-aaf7cbe0a801
Lester, David
be34b678-d6ce-4342-a494-1dad2aaafd75
May 2012
Brown, Andrew D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Reeve, Jeffrey
dd909010-7d44-44ea-83fe-a09e4d492618
Furber, Stephen
e9e61fb3-2bb8-45be-9f39-aaf7cbe0a801
Lester, David
be34b678-d6ce-4342-a494-1dad2aaafd75
Brown, Andrew D., Reeve, Jeffrey, Furber, Stephen and Lester, David
(2012)
Processing with a million cores.
De Bosschere, Koen, D'Hollander, Gerhard R., Padua, David, Peters, Frans and Sawyer, Mark
(eds.)
In Applications, Tools and Techniques on the Road to Exascale Computing.
vol. 22,
IOS Press.
.
(doi:10.3233/978-1-61499-041-3-327).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Traditionally, the performance-limiting attributes of a multi-processor machine are memory bandwidth, the need to maintain state coherence, and simple synchronisation issues, or some combination of these. As the system size increases, so too does the relative cost overhead of solving these problems. The SpiNNaker engine is a million core system with over eight terabytes of distributed memory whose fundamental design axioms neatly sidestep these problems: the processors are not synchronised, the memory is not coherent, and the inter-processor communication is non-deterministic. How, then, can we perform meaningful computations with this architecture?
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Published date: May 2012
Venue - Dates:
14th Biennial ParCo Conference, ParCo2011, Ghent, Belgium, 2012-05-01
Organisations:
Electronics & Computer Science
Identifiers
Local EPrints ID: 340123
URI: http://eprints.soton.ac.uk/id/eprint/340123
ISBN: 978-1-61499-040-6
PURE UUID: 2743568a-0621-423c-b92c-587885f32940
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Date deposited: 12 Jun 2012 10:13
Last modified: 14 Mar 2024 11:19
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Contributors
Author:
Andrew D. Brown
Author:
Jeffrey Reeve
Author:
Stephen Furber
Author:
David Lester
Editor:
Koen De Bosschere
Editor:
Gerhard R. D'Hollander
Editor:
David Padua
Editor:
Frans Peters
Editor:
Mark Sawyer
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