Mistry, Jatin N., Biggs, John, Myers, James, Al-Hashimi, Bashir M. and Flynn, David
dRail: a novel physical layout methodology for power gated circuits
At Power and Timing Modelling, Optimization and Simulation (PATMOS) 2012, United Kingdom.
04 - 06 Sep 2012.
In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 processor using a 65nm library, and shows up to 38% reduction in area cost when compared to traditional voltage area layout
Conference or Workshop Item
|Venue - Dates:
||Power and Timing Modelling, Optimization and Simulation (PATMOS) 2012, United Kingdom, 2012-09-04 - 2012-09-06
||Electronic & Software Systems
|8 August 2012||Published|
||08 Aug 2012 14:06
||17 Apr 2017 16:43
|Further Information:||Google Scholar|
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