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dRail: a novel physical layout methodology for power gated circuits

Mistry, Jatin N., Biggs, John, Myers, James, Al-Hashimi, Bashir M. and Flynn, David (2012) dRail: a novel physical layout methodology for power gated circuits At Power and Timing Modelling, Optimization and Simulation (PATMOS) 2012, United Kingdom. 04 - 06 Sep 2012. 10 pp.

Record type: Conference or Workshop Item (Paper)

Abstract

In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 processor using a 65nm library, and shows up to 38% reduction in area cost when compared to traditional voltage area layout

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More information

Published date: 8 August 2012
Venue - Dates: Power and Timing Modelling, Optimization and Simulation (PATMOS) 2012, United Kingdom, 2012-09-04 - 2012-09-06
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 341944
URI: http://eprints.soton.ac.uk/id/eprint/341944
PURE UUID: 3d2214a0-4d91-4589-aa1a-707fea6f1cb8

Catalogue record

Date deposited: 08 Aug 2012 14:06
Last modified: 18 Jul 2017 05:31

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Contributors

Author: Jatin N. Mistry
Author: John Biggs
Author: James Myers
Author: David Flynn

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