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SETTOFF : a fault tolerant flip-flop for building cost-efficient reliable systems

Lin, Yang and Zwolinski, Mark (2012) SETTOFF : a fault tolerant flip-flop for building cost-efficient reliable systems At IOLTS 2012: 18th IEEE International On-Line Testing Symposium, Spain. 27 - 29 Jun 2012.

Record type: Conference or Workshop Item (Paper)

Abstract

Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. The result indicates that SETTOFF is suitable for building high reliable systems at lower cost than the traditional techniques.

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More information

Published date: 27 June 2012
Venue - Dates: IOLTS 2012: 18th IEEE International On-Line Testing Symposium, Spain, 2012-06-27 - 2012-06-29
Organisations: EEE

Identifiers

Local EPrints ID: 341995
URI: http://eprints.soton.ac.uk/id/eprint/341995
PURE UUID: 31f5f28e-605e-45b7-8bf8-e2cffbfe120f
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 09 Aug 2012 11:17
Last modified: 18 Jul 2017 05:31

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Contributors

Author: Yang Lin
Author: Mark Zwolinski ORCID iD

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