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Active mode subclock power gating

Mistry, Jatin, Myers, James, Al-Hashimi, Bashir, Flynn, David, Biggs, John and Merrett, Geoff V. (2013) Active mode subclock power gating IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-11. (doi:10.1109/TVLSI.2013.2280886).

Record type: Article


This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than Vth rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of nMOS and pMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The subclock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor, which was fabricated in a 65-nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared with the same microprocessor without subclock power gating.

PDF Active_Mode_Sub-Clock_Power_Gating.pdf - Accepted Manuscript
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e-pub ahead of print date: 20 September 2013
Organisations: Electronic & Software Systems


Local EPrints ID: 346259
ISSN: 1063-8210
PURE UUID: 1814784e-6347-4eb2-8da9-25c77cad3b5e
ORCID for Geoff V. Merrett: ORCID iD

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Date deposited: 18 Dec 2012 18:45
Last modified: 24 Jul 2017 16:40

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Author: Jatin Mistry
Author: James Myers
Author: David Flynn
Author: John Biggs
Author: Geoff V. Merrett ORCID iD

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