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Active mode subclock power gating

Active mode subclock power gating
Active mode subclock power gating
This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than Vth rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of nMOS and pMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The subclock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor, which was fabricated in a 65-nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared with the same microprocessor without subclock power gating.
1063-8210
1-11
Mistry, Jatin
33aed46c-96bc-4c24-8c7d-a5d404dfd3cc
Myers, James
b541d1fd-a24a-4771-91b3-84e1ac8c7fe5
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Biggs, John
78ae4037-2e29-49dd-b2cc-e7e3885fc008
Merrett, Geoff V.
89b3a696-41de-44c3-89aa-b0aa29f54020
Mistry, Jatin
33aed46c-96bc-4c24-8c7d-a5d404dfd3cc
Myers, James
b541d1fd-a24a-4771-91b3-84e1ac8c7fe5
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Biggs, John
78ae4037-2e29-49dd-b2cc-e7e3885fc008
Merrett, Geoff V.
89b3a696-41de-44c3-89aa-b0aa29f54020

Mistry, Jatin, Myers, James, Al-Hashimi, Bashir, Flynn, David, Biggs, John and Merrett, Geoff V. (2013) Active mode subclock power gating. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-11. (doi:10.1109/TVLSI.2013.2280886).

Record type: Article

Abstract

This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than Vth rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of nMOS and pMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The subclock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor, which was fabricated in a 65-nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared with the same microprocessor without subclock power gating.

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Active_Mode_Sub-Clock_Power_Gating.pdf - Accepted Manuscript
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More information

e-pub ahead of print date: 20 September 2013
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 346259
URI: http://eprints.soton.ac.uk/id/eprint/346259
ISSN: 1063-8210
PURE UUID: 1814784e-6347-4eb2-8da9-25c77cad3b5e
ORCID for Geoff V. Merrett: ORCID iD orcid.org/0000-0003-4980-3894

Catalogue record

Date deposited: 18 Dec 2012 18:45
Last modified: 15 Mar 2024 03:23

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Contributors

Author: Jatin Mistry
Author: James Myers
Author: Bashir Al-Hashimi
Author: David Flynn
Author: John Biggs
Author: Geoff V. Merrett ORCID iD

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