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Delay test for diagnosis of power switches

Delay test for diagnosis of power switches
Delay test for diagnosis of power switches
Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosing
power switches. The proposed diagnosis method utilizes recently proposed DFT solution for efficient testing of power switches in the presence of PVT variation. It divides power switches into segments such that any faulty power switch is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; and the worst case loss of accuracy is less than 12% when considering VT (Voltage and Temperature) variations.
sleep transistor, diagnosis, power gating, leakage power management, design for test (dft)
1063-8210
1-10
Khursheed, Syed Saqib
df76c622-61ca-45b2-b067-2753f1ac0abf
Shi, Kan
32027f24-8b6e-4a52-af6b-5320a3d70581
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Wilson, Peter R.
8a65c092-c197-4f43-b8fc-e12977783cb3
Chakrabarty, Krishnendu
a8afcb71-145f-4def-ac52-e03ecc47863f
Khursheed, Syed Saqib
df76c622-61ca-45b2-b067-2753f1ac0abf
Shi, Kan
32027f24-8b6e-4a52-af6b-5320a3d70581
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Wilson, Peter R.
8a65c092-c197-4f43-b8fc-e12977783cb3
Chakrabarty, Krishnendu
a8afcb71-145f-4def-ac52-e03ecc47863f

Khursheed, Syed Saqib, Shi, Kan, Al-Hashimi, Bashir, Wilson, Peter R. and Chakrabarty, Krishnendu (2013) Delay test for diagnosis of power switches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, n/a, 1-10. (doi:10.1109/TVLSI.2013.2239319).

Record type: Article

Abstract

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosing
power switches. The proposed diagnosis method utilizes recently proposed DFT solution for efficient testing of power switches in the presence of PVT variation. It divides power switches into segments such that any faulty power switch is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; and the worst case loss of accuracy is less than 12% when considering VT (Voltage and Temperature) variations.

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More information

e-pub ahead of print date: January 2013
Keywords: sleep transistor, diagnosis, power gating, leakage power management, design for test (dft)
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 346835
URI: http://eprints.soton.ac.uk/id/eprint/346835
ISSN: 1063-8210
PURE UUID: 275a3820-9737-4f57-b889-2911f4d6f0c5

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Date deposited: 15 Jan 2013 15:31
Last modified: 11 Nov 2019 20:59

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