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MALEC: a multiple access low energy cache

MALEC: a multiple access low energy cache
MALEC: a multiple access low energy cache
This paper addresses the dynamic energy consumption in L1 data cache interfaces of out-of-order superscalar processors. The proposed Multiple Access Low Energy Cache (MALEC) is based on the observation that consecutive memory references tend to access the same page. It exhibits a performance level similar to state of the art caches, but consumes approximately 48% less energy. This is achieved by deliberately restricting accesses to only 1 page per cycle, allowing the utilization of single-ported TLBs and cache banks, and simplified lookup structures of Store and Merge Buffers. To mitigate performance penalties it shares memory address translation results between multiple memory references, and shares data among loads to the same cache line. In addition, it uses a Page-Based Way Determination scheme that holds way information of recently accessed cache lines in small storage structures called way tables that are closely coupled to TLB lookups and are able to simultaneously service all accesses to a particular page. Moreover, it removes the need for redundant tag-array accesses, usually required to confirm way predictions.

For the analyzed workloads, MALEC achieves average energy savings of 48% in the L1 data memory subsystem over a high performance cache interface that supports up to 2 loads and 1 store in parallel. Comparing MALEC and the high performance interface against a low power configuration limited to only 1 load or 1 store per cycle reveals 14% and 15% performance gain requiring 22% less and 48% more energy, respectively. Furthermore, Page-Based Way Determination exhibits coverage of 94%, which is a 16% improvement over the originally proposed line-based way determination.
Boettcher, Matthias
d34d0210-df72-4f89-ad87-91d87a4f272a
Gabrielli, Giacomo
79e841c7-f0b2-48bb-81b0-9aba55fac63f
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Kershaw, Danny
bcffdd48-bb1a-416f-a5c7-c04e4259794f
Boettcher, Matthias
d34d0210-df72-4f89-ad87-91d87a4f272a
Gabrielli, Giacomo
79e841c7-f0b2-48bb-81b0-9aba55fac63f
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Kershaw, Danny
bcffdd48-bb1a-416f-a5c7-c04e4259794f

Boettcher, Matthias, Gabrielli, Giacomo, Al-Hashimi, Bashir M. and Kershaw, Danny (2013) MALEC: a multiple access low energy cache. DATE2013: Design Automation and Test Conference in Europe, France. 19 - 22 Mar 2013. 6 pp .

Record type: Conference or Workshop Item (Paper)

Abstract

This paper addresses the dynamic energy consumption in L1 data cache interfaces of out-of-order superscalar processors. The proposed Multiple Access Low Energy Cache (MALEC) is based on the observation that consecutive memory references tend to access the same page. It exhibits a performance level similar to state of the art caches, but consumes approximately 48% less energy. This is achieved by deliberately restricting accesses to only 1 page per cycle, allowing the utilization of single-ported TLBs and cache banks, and simplified lookup structures of Store and Merge Buffers. To mitigate performance penalties it shares memory address translation results between multiple memory references, and shares data among loads to the same cache line. In addition, it uses a Page-Based Way Determination scheme that holds way information of recently accessed cache lines in small storage structures called way tables that are closely coupled to TLB lookups and are able to simultaneously service all accesses to a particular page. Moreover, it removes the need for redundant tag-array accesses, usually required to confirm way predictions.

For the analyzed workloads, MALEC achieves average energy savings of 48% in the L1 data memory subsystem over a high performance cache interface that supports up to 2 loads and 1 store in parallel. Comparing MALEC and the high performance interface against a low power configuration limited to only 1 load or 1 store per cycle reveals 14% and 15% performance gain requiring 22% less and 48% more energy, respectively. Furthermore, Page-Based Way Determination exhibits coverage of 94%, which is a 16% improvement over the originally proposed line-based way determination.

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More information

Published date: March 2013
Venue - Dates: DATE2013: Design Automation and Test Conference in Europe, France, 2013-03-19 - 2013-03-22
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 347147
URI: https://eprints.soton.ac.uk/id/eprint/347147
PURE UUID: 5236444f-3078-459f-8cf7-9557e2b80f43

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Date deposited: 07 Feb 2013 12:15
Last modified: 18 Jul 2017 04:59

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