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Improved state integrity of flip-flops for voltage scaled retention under PVT variation

Yang, Sheng, Khursheed, Saqib, Al-Hashimi, Bashir M., Flynn, David and Merrett, Geoff V. (2013) Improved state integrity of flip-flops for voltage scaled retention under PVT variation IEEE Transactions on Circuits and Systems I: Regular Papers, 60, (11), pp. 1-9. (doi:10.1109/TCSI.2013.2252640).

Record type: Article

Abstract

Through measurements from 82 test chips, each with a state retention block of 8192 flip-flops, implemented using 65-nm design library, we demonstrate that state integrity of a flip-flop is sensitive to process, voltage, and temperature (PVT) variation. It has been found at 25?C that First Failure Voltage (FFV) of flip-flops varies from die to die, ranging from 245-mV to 315-mV, with 79% of total dies exhibiting single bit failure at FFV, while the rest show multi-bit failure. In terms of temperature variation, it has been found that FFV increases by up to 30-mV with increase in temperature from 25?C to 79?C, demonstrating its sensitivity to temperature variation. This work proposes a PVT-aware state-protection technique to ensure state integrity of flip-flops, while achieving maximum leakage savings. The proposed technique consists of characterization algorithm to determine minimum state retention voltage (MRV) of each die, and employs horizontal and vertical parity for error detection and single bit error correction. In case of error detection, it dynamically adjusts MRV per die to avoid subsequent errors. Silicon results show that at characterized MRV, flip-flop state integrity is preserved, while achieving up to 17.6% reduction in retention voltage across 82-dies.

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e-pub ahead of print date: 2 April 2013
Keywords: state integrity, state retention, voltage scaling, online error detection and correction, leakage power reduction
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 348727
URI: http://eprints.soton.ac.uk/id/eprint/348727
ISSN: 1549-8328
PURE UUID: 31793cc3-1dfd-45f3-9722-68a62758621b
ORCID for Geoff V. Merrett: ORCID iD orcid.org/0000-0003-4980-3894

Catalogue record

Date deposited: 18 Feb 2013 15:37
Last modified: 24 Jul 2017 16:40

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Contributors

Author: Sheng Yang
Author: Saqib Khursheed
Author: David Flynn
Author: Geoff V. Merrett ORCID iD

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