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SpiNNaker: a 1-W 18-core system-on-chip for massively parallel neural network simulation

Painkras, Eustace, Plana, Luis, Garside, Jim, Temple, Steve, Galluppi, Francesco, Patterson, Cameron, Lester, David, Brown, Andrew D. and Furber, Steve B. (2013) SpiNNaker: a 1-W 18-core system-on-chip for massively parallel neural network simulation IEEE Journal of Solid State Circuits, 48, (8), pp. 1943-1953. (doi:10.1109/JSSC.2013.2259038).

Record type: Article

Abstract

The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements

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Published date: August 2013
Keywords: chip multiprocessor, energy-efficiency, asynchronous interconnect, gals, network-on-chip, neuromorphichardware, spiking neural networks, real-time simulation
Organisations: EEE

Identifiers

Local EPrints ID: 350493
URI: http://eprints.soton.ac.uk/id/eprint/350493
ISSN: 0018-9200
PURE UUID: 2f331656-3e3e-400b-9b13-99f066e73ae7

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Date deposited: 25 Mar 2013 17:34
Last modified: 07 Aug 2017 13:45

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Contributors

Author: Eustace Painkras
Author: Luis Plana
Author: Jim Garside
Author: Steve Temple
Author: Francesco Galluppi
Author: Cameron Patterson
Author: David Lester
Author: Andrew D. Brown
Author: Steve B. Furber

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