STEP: a unified design methodology for secure test and IP core protection
STEP: a unified design methodology for secure test and IP core protection
Intellectual property (IP) core based embedded systems design is a pervasive practice in the semiconductor industry due to shorter time-to-market and tougher cost competitions. Protecting the design information in these IP cores and securing test from various attacks are two emerging challenges in today's embedded systems design. Recently reported techniques address these challenges considering secure test and IP core protection separately. However, for ensuring high security during IP core functionality and also during test, joint consideration of secure test and IP core protection is much needed. In this paper, we propose a novel and unified design methodology, called STEP (Secure TEst and IP core Protection), which addresses the joint objective of secure test and IP core protection. The aim of STEP design methodology is to achieve high security at low system cost using the same key integrated hardware during test and IP core functionality. We evaluate the effectiveness of STEP design methodology considering advanced encryption standard (AES) system as a case study. We show that proposed design methodology benefits from high security and test accuracy, requiring up to 9% higher area and 20% power overheads
978-1-4503-1244-8
333-338
Yeolekar, Pranav
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Shafik, Rishad A
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Mathew, Jimson
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Pradhan, Dhiraj K
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Mohanty, Saraju P
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2012
Yeolekar, Pranav
2ca7ab84-3ebd-4cd3-9853-f16cf836fd4e
Shafik, Rishad A
aa0bdafc-b022-4cb2-a8ef-4bf8a03ba524
Mathew, Jimson
156eec1e-d690-43eb-a72f-daefd8b04144
Pradhan, Dhiraj K
78edbd6a-a8c0-4db0-951f-d88c687ec8a1
Mohanty, Saraju P
5e933cb9-dac5-47af-87c2-5871d2a9b42c
Yeolekar, Pranav, Shafik, Rishad A, Mathew, Jimson, Pradhan, Dhiraj K and Mohanty, Saraju P
(2012)
STEP: a unified design methodology for secure test and IP core protection.
GLSVLSI 2012, Salt Lake City, United States.
03 - 04 May 2012.
.
(doi:10.1145/2206781.2206862).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Intellectual property (IP) core based embedded systems design is a pervasive practice in the semiconductor industry due to shorter time-to-market and tougher cost competitions. Protecting the design information in these IP cores and securing test from various attacks are two emerging challenges in today's embedded systems design. Recently reported techniques address these challenges considering secure test and IP core protection separately. However, for ensuring high security during IP core functionality and also during test, joint consideration of secure test and IP core protection is much needed. In this paper, we propose a novel and unified design methodology, called STEP (Secure TEst and IP core Protection), which addresses the joint objective of secure test and IP core protection. The aim of STEP design methodology is to achieve high security at low system cost using the same key integrated hardware during test and IP core functionality. We evaluate the effectiveness of STEP design methodology considering advanced encryption standard (AES) system as a case study. We show that proposed design methodology benefits from high security and test accuracy, requiring up to 9% higher area and 20% power overheads
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More information
Published date: 2012
Venue - Dates:
GLSVLSI 2012, Salt Lake City, United States, 2012-05-03 - 2012-05-04
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 353383
URI: http://eprints.soton.ac.uk/id/eprint/353383
ISBN: 978-1-4503-1244-8
PURE UUID: e448304c-88e6-42a6-8bc7-2c91b06ddc07
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Date deposited: 10 Jun 2013 14:24
Last modified: 14 Mar 2024 14:04
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Contributors
Author:
Pranav Yeolekar
Author:
Rishad A Shafik
Author:
Jimson Mathew
Author:
Dhiraj K Pradhan
Author:
Saraju P Mohanty
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