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A proposal for hybrid memristor-CMOS spiking neuromorphic learning systems

A proposal for hybrid memristor-CMOS spiking neuromorphic learning systems
A proposal for hybrid memristor-CMOS spiking neuromorphic learning systems
Recent research in nanotechnology has led to the practical realization of nanoscale devices that behave as memristors, a device that was postulated in the seventies by Chua based on circuit theoretical reasonings. On the other hand, neuromorphic engineering, a discipline that implements physical artifacts based on neuroscience knowledge, has related neural learning mechanisms to the operation of memristors. As a result, neuro-inspired learning architectures can be proposed that exploit nanoscale memristors for building very large scale systems with very dense synaptic-like memory elements. At present, the deep understanding of the internal mechanisms governing memristor operation is still an open issue, and the practical realization of very large scale and reliable "memristive fabric" for neural learning applications is not a reality yet. However, in the meantime, researchers are proposing and analyzing potential circuit architectures that would combine a standard CMOS substrate with a memristive nanoscale fabric on top to realize hybrid memristor-CMOS neural learning systems. The focus of this paper is on one such architecture for implementing the very well established Spike-Timing-Dependent-Plasticity (STDP) learning mechanism found in biology. In this paper we quickly review spiking neural systems, STDP learning, and memristors, and propose a hybrid memristor-CMOS system architecture with the potential of implementing a large scale STDP learning spiking neural system. Such architecture would eventually allow to implement real-time brain-like processing learning systems with about neurons and synapses on one single Printed Circuit Board (PCB).
1531-636X
74-88
Serrano-Gotarredona, T.
8a2751a4-8752-46e3-8a64-1e82eeb84f1f
Prodromakis, T.
d58c9c10-9d25-4d22-b155-06c8437acfbf
Linares-Barranco, B.
3f44925c-96cb-48ac-a83c-a781e264bd3c
Serrano-Gotarredona, T.
8a2751a4-8752-46e3-8a64-1e82eeb84f1f
Prodromakis, T.
d58c9c10-9d25-4d22-b155-06c8437acfbf
Linares-Barranco, B.
3f44925c-96cb-48ac-a83c-a781e264bd3c

Serrano-Gotarredona, T., Prodromakis, T. and Linares-Barranco, B. (2013) A proposal for hybrid memristor-CMOS spiking neuromorphic learning systems. IEEE Circuits and Systems Magazine, 13 (2), 74-88. (doi:10.1109/MCAS.2013.2256271).

Record type: Article

Abstract

Recent research in nanotechnology has led to the practical realization of nanoscale devices that behave as memristors, a device that was postulated in the seventies by Chua based on circuit theoretical reasonings. On the other hand, neuromorphic engineering, a discipline that implements physical artifacts based on neuroscience knowledge, has related neural learning mechanisms to the operation of memristors. As a result, neuro-inspired learning architectures can be proposed that exploit nanoscale memristors for building very large scale systems with very dense synaptic-like memory elements. At present, the deep understanding of the internal mechanisms governing memristor operation is still an open issue, and the practical realization of very large scale and reliable "memristive fabric" for neural learning applications is not a reality yet. However, in the meantime, researchers are proposing and analyzing potential circuit architectures that would combine a standard CMOS substrate with a memristive nanoscale fabric on top to realize hybrid memristor-CMOS neural learning systems. The focus of this paper is on one such architecture for implementing the very well established Spike-Timing-Dependent-Plasticity (STDP) learning mechanism found in biology. In this paper we quickly review spiking neural systems, STDP learning, and memristors, and propose a hybrid memristor-CMOS system architecture with the potential of implementing a large scale STDP learning spiking neural system. Such architecture would eventually allow to implement real-time brain-like processing learning systems with about neurons and synapses on one single Printed Circuit Board (PCB).

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More information

Published date: 22 May 2013
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 353406
URI: https://eprints.soton.ac.uk/id/eprint/353406
ISSN: 1531-636X
PURE UUID: 2e4b46ce-7f62-4743-aed6-a3ea3ba847a6
ORCID for T. Prodromakis: ORCID iD orcid.org/0000-0002-6267-6909

Catalogue record

Date deposited: 06 Jun 2013 07:57
Last modified: 06 Jul 2018 00:29

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